Merge branch 'drm-next-4.10' of git://people.freedesktop.org/~agd5f/linux into drm-next

First new feature pull for 4.10.  Highlights:
- Support for multple virtual displays in the virtual dce component
- New VM mgr to support non-contiguous vram buffers
- Support for UVD powergating on additional asics
- Power management improvements
- lots of code cleanup and bug fixes

* 'drm-next-4.10' of git://people.freedesktop.org/~agd5f/linux: (107 commits)
  drm/amdgpu: turn on/off uvd clock when dpm enable/disable on CI
  drm/amdgpu: disable dpm before turn off clock when vce idle.
  drm/amdgpu: enable uvd bypass mode for CI/VI.
  drm/amdgpu: just not load smc firmware if smu is already running
  drm/amdgpu: when suspend, set boot state instand of disable dpm.
  drm/amdgpu: use failed label to handle context init failure
  drm/amdgpu: add amdgpu_ttm_bo_eviction_valuable callback
  drm/ttm: make eviction decision a driver callback v2
  drm/ttm: fix coding style in ttm_bo_driver.h
  drm/radeon/pm: autoswitch power state when in balanced mode
  drm/amd/powerplay: fix spelling mistake and add KERN_WARNING to printks
  drm/amdgpu:new ids flag for preempt
  drm/amdgpu: mark symbols static where possible
  drm/amdgpu: change function declarations and add missing header dependencies
  drm/amdgpu: s/amdgpuCrtc/amdgpu_crtc/ in pageflip code
  drm/amdgpu/atom: remove a bunch of unused functions
  drm/amdgpu: consolidate atom scratch reg handling for hangs
  drm/amdgpu: use amdgpu_bo_[create|free]_kernel for wb
  drm/amdgpu: add VCE VM session tracking
  drm/amdgpu: improve parse_cs handling a bit
  ...

1 files changed, 39 insertions, 2 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index cb3d252f3c78..0f0b38191fac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -228,6 +228,9 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_firmware_info *ucode,
         ucode->mc_addr = mc_addr;
         ucode->kaddr = kptr;
 
+        if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE)
+                return 0;
+
         header = (const struct common_firmware_header *)ucode->fw->data;
         memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
                 le32_to_cpu(header->ucode_array_offset_bytes)),
@@ -236,6 +239,31 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_firmware_info *ucode,
         return 0;
 }
 
+static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
+                                uint64_t mc_addr, void *kptr)
+{
+        const struct gfx_firmware_header_v1_0 *header = NULL;
+        const struct common_firmware_header *comm_hdr = NULL;
+        uint8_t* src_addr = NULL;
+        uint8_t* dst_addr = NULL;
+
+        if (NULL == ucode->fw)
+                return 0;
+
+        comm_hdr = (const struct common_firmware_header *)ucode->fw->data;
+        header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
+        dst_addr = ucode->kaddr +
+                           ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes),
+                           PAGE_SIZE);
+        src_addr = (uint8_t *)ucode->fw->data +
+                           le32_to_cpu(comm_hdr->ucode_array_offset_bytes) +
+                           (le32_to_cpu(header->jt_offset) * 4);
+        memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4);
+
+        return 0;
+}
+
+
 int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
 {
         struct amdgpu_bo **bo = &adev->firmware.fw_buf;
@@ -247,7 +275,8 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
         const struct common_firmware_header *header = NULL;
 
         err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true,
-                               AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, bo);
+                                amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
+                                0, NULL, NULL, bo);
         if (err) {
                 dev_err(adev->dev, "(%d) Firmware buffer allocate failed\n", err);
                 goto failed;
@@ -259,7 +288,8 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
                 goto failed_reserve;
         }
 
-        err = amdgpu_bo_pin(*bo, AMDGPU_GEM_DOMAIN_GTT, &fw_mc_addr);
+        err = amdgpu_bo_pin(*bo, amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
+                                &fw_mc_addr);
         if (err) {
                 dev_err(adev->dev, "(%d) Firmware buffer pin failed\n", err);
                 goto failed_pin;
@@ -279,6 +309,13 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
                         header = (const struct common_firmware_header *)ucode->fw->data;
                         amdgpu_ucode_init_single_fw(ucode, fw_mc_addr + fw_offset,
                                                     fw_buf_ptr + fw_offset);
+                        if (i == AMDGPU_UCODE_ID_CP_MEC1) {
+                                const struct gfx_firmware_header_v1_0 *cp_hdr;
+                                cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
+                                amdgpu_ucode_patch_jt(ucode, fw_mc_addr + fw_offset,
+                                                    fw_buf_ptr + fw_offset);
+                                fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
+                        }
                         fw_offset += ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
                 }
         }