diff options
| author | Thomas Gleixner <tglx@linutronix.de> | 2017-11-23 10:29:05 -0500 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2017-11-23 10:29:05 -0500 |
| commit | 866c9b94ef968445c52214b3748ecc52a8491bca (patch) | |
| tree | 1fd073acb9be8e89e77b35c41e2964ac6feabee6 /drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | |
| parent | aea3706cfc4d952ed6d32b6d5845b5ecd99ed7f5 (diff) | |
| parent | 841b86f3289dbe858daeceec36423d4ea286fac2 (diff) | |
Merge tag 'for-linus-timers-conversion-final-v4.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux into timers/urgent
Pull the last batch of manual timer conversions from Kees Cook:
- final batch of "non trivial" timer conversions (multi-tree dependencies,
things Coccinelle couldn't handle, etc).
- treewide conversions via Coccinelle, in 4 steps:
- DEFINE_TIMER() functions converted to struct timer_list * argument
- init_timer() -> setup_timer()
- setup_timer() -> timer_setup()
- setup_timer() -> timer_setup() (with a single embedded structure)
- deprecated timer API removals (init_timer(), setup_*timer())
- finalization of new API (remove global casts)
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 70 |
1 files changed, 33 insertions, 37 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index 36c763310df5..65649026b836 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | |||
| @@ -270,12 +270,8 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) | |||
| 270 | else | 270 | else |
| 271 | return AMDGPU_FW_LOAD_SMU; | 271 | return AMDGPU_FW_LOAD_SMU; |
| 272 | case CHIP_VEGA10: | 272 | case CHIP_VEGA10: |
| 273 | if (!load_type) | ||
| 274 | return AMDGPU_FW_LOAD_DIRECT; | ||
| 275 | else | ||
| 276 | return AMDGPU_FW_LOAD_PSP; | ||
| 277 | case CHIP_RAVEN: | 273 | case CHIP_RAVEN: |
| 278 | if (load_type != 2) | 274 | if (!load_type) |
| 279 | return AMDGPU_FW_LOAD_DIRECT; | 275 | return AMDGPU_FW_LOAD_DIRECT; |
| 280 | else | 276 | else |
| 281 | return AMDGPU_FW_LOAD_PSP; | 277 | return AMDGPU_FW_LOAD_PSP; |
| @@ -364,8 +360,6 @@ static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode, | |||
| 364 | int amdgpu_ucode_init_bo(struct amdgpu_device *adev) | 360 | int amdgpu_ucode_init_bo(struct amdgpu_device *adev) |
| 365 | { | 361 | { |
| 366 | struct amdgpu_bo **bo = &adev->firmware.fw_buf; | 362 | struct amdgpu_bo **bo = &adev->firmware.fw_buf; |
| 367 | uint64_t fw_mc_addr; | ||
| 368 | void *fw_buf_ptr = NULL; | ||
| 369 | uint64_t fw_offset = 0; | 363 | uint64_t fw_offset = 0; |
| 370 | int i, err; | 364 | int i, err; |
| 371 | struct amdgpu_firmware_info *ucode = NULL; | 365 | struct amdgpu_firmware_info *ucode = NULL; |
| @@ -376,37 +370,39 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev) | |||
| 376 | return 0; | 370 | return 0; |
| 377 | } | 371 | } |
| 378 | 372 | ||
| 379 | err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true, | 373 | if (!amdgpu_sriov_vf(adev) || !adev->in_sriov_reset) { |
| 380 | amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, | 374 | err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true, |
| 381 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, | 375 | amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, |
| 382 | NULL, NULL, 0, bo); | 376 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, |
| 383 | if (err) { | 377 | NULL, NULL, 0, bo); |
| 384 | dev_err(adev->dev, "(%d) Firmware buffer allocate failed\n", err); | 378 | if (err) { |
| 385 | goto failed; | 379 | dev_err(adev->dev, "(%d) Firmware buffer allocate failed\n", err); |
| 386 | } | 380 | goto failed; |
| 381 | } | ||
| 387 | 382 | ||
| 388 | err = amdgpu_bo_reserve(*bo, false); | 383 | err = amdgpu_bo_reserve(*bo, false); |
| 389 | if (err) { | 384 | if (err) { |
| 390 | dev_err(adev->dev, "(%d) Firmware buffer reserve failed\n", err); | 385 | dev_err(adev->dev, "(%d) Firmware buffer reserve failed\n", err); |
| 391 | goto failed_reserve; | 386 | goto failed_reserve; |
| 392 | } | 387 | } |
| 393 | 388 | ||
| 394 | err = amdgpu_bo_pin(*bo, amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, | 389 | err = amdgpu_bo_pin(*bo, amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, |
| 395 | &fw_mc_addr); | 390 | &adev->firmware.fw_buf_mc); |
| 396 | if (err) { | 391 | if (err) { |
| 397 | dev_err(adev->dev, "(%d) Firmware buffer pin failed\n", err); | 392 | dev_err(adev->dev, "(%d) Firmware buffer pin failed\n", err); |
| 398 | goto failed_pin; | 393 | goto failed_pin; |
| 399 | } | 394 | } |
| 400 | 395 | ||
| 401 | err = amdgpu_bo_kmap(*bo, &fw_buf_ptr); | 396 | err = amdgpu_bo_kmap(*bo, &adev->firmware.fw_buf_ptr); |
| 402 | if (err) { | 397 | if (err) { |
| 403 | dev_err(adev->dev, "(%d) Firmware buffer kmap failed\n", err); | 398 | dev_err(adev->dev, "(%d) Firmware buffer kmap failed\n", err); |
| 404 | goto failed_kmap; | 399 | goto failed_kmap; |
| 405 | } | 400 | } |
| 406 | 401 | ||
| 407 | amdgpu_bo_unreserve(*bo); | 402 | amdgpu_bo_unreserve(*bo); |
| 403 | } | ||
| 408 | 404 | ||
| 409 | memset(fw_buf_ptr, 0, adev->firmware.fw_size); | 405 | memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size); |
| 410 | 406 | ||
| 411 | /* | 407 | /* |
| 412 | * if SMU loaded firmware, it needn't add SMC, UVD, and VCE | 408 | * if SMU loaded firmware, it needn't add SMC, UVD, and VCE |
| @@ -425,14 +421,14 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev) | |||
| 425 | ucode = &adev->firmware.ucode[i]; | 421 | ucode = &adev->firmware.ucode[i]; |
| 426 | if (ucode->fw) { | 422 | if (ucode->fw) { |
| 427 | header = (const struct common_firmware_header *)ucode->fw->data; | 423 | header = (const struct common_firmware_header *)ucode->fw->data; |
| 428 | amdgpu_ucode_init_single_fw(adev, ucode, fw_mc_addr + fw_offset, | 424 | amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset, |
| 429 | (void *)((uint8_t *)fw_buf_ptr + fw_offset)); | 425 | adev->firmware.fw_buf_ptr + fw_offset); |
| 430 | if (i == AMDGPU_UCODE_ID_CP_MEC1 && | 426 | if (i == AMDGPU_UCODE_ID_CP_MEC1 && |
| 431 | adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { | 427 | adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { |
| 432 | const struct gfx_firmware_header_v1_0 *cp_hdr; | 428 | const struct gfx_firmware_header_v1_0 *cp_hdr; |
| 433 | cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; | 429 | cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; |
| 434 | amdgpu_ucode_patch_jt(ucode, fw_mc_addr + fw_offset, | 430 | amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset, |
| 435 | fw_buf_ptr + fw_offset); | 431 | adev->firmware.fw_buf_ptr + fw_offset); |
| 436 | fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE); | 432 | fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE); |
| 437 | } | 433 | } |
| 438 | fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE); | 434 | fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE); |
