diff options
| author | Sean Paul <seanpaul@chromium.org> | 2018-09-27 02:54:54 -0400 |
|---|---|---|
| committer | Sean Paul <seanpaul@chromium.org> | 2018-09-27 02:54:54 -0400 |
| commit | 7b76d0588477d4b6097a9048b42835a45caf5c48 (patch) | |
| tree | fa4e0bcd49f8d17f26795224290c8f8460aa4116 /drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | |
| parent | a74c0aa524050e5fd6c275a153b1f37283f6e37c (diff) | |
| parent | bf78296ab1cb215d0609ac6cff4e43e941e51265 (diff) | |
Merge drm/drm-next into drm-misc-next
Backmerging 4.19-rc5 to pick up sun4i fix
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 25 |
1 files changed, 21 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index f55f72a37ca8..1fa8bc337859 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | |||
| @@ -277,6 +277,7 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) | |||
| 277 | case CHIP_PITCAIRN: | 277 | case CHIP_PITCAIRN: |
| 278 | case CHIP_VERDE: | 278 | case CHIP_VERDE: |
| 279 | case CHIP_OLAND: | 279 | case CHIP_OLAND: |
| 280 | case CHIP_HAINAN: | ||
| 280 | return AMDGPU_FW_LOAD_DIRECT; | 281 | return AMDGPU_FW_LOAD_DIRECT; |
| 281 | #endif | 282 | #endif |
| 282 | #ifdef CONFIG_DRM_AMDGPU_CIK | 283 | #ifdef CONFIG_DRM_AMDGPU_CIK |
| @@ -303,12 +304,11 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) | |||
| 303 | case CHIP_VEGA10: | 304 | case CHIP_VEGA10: |
| 304 | case CHIP_RAVEN: | 305 | case CHIP_RAVEN: |
| 305 | case CHIP_VEGA12: | 306 | case CHIP_VEGA12: |
| 307 | case CHIP_VEGA20: | ||
| 306 | if (!load_type) | 308 | if (!load_type) |
| 307 | return AMDGPU_FW_LOAD_DIRECT; | 309 | return AMDGPU_FW_LOAD_DIRECT; |
| 308 | else | 310 | else |
| 309 | return AMDGPU_FW_LOAD_PSP; | 311 | return AMDGPU_FW_LOAD_PSP; |
| 310 | case CHIP_VEGA20: | ||
| 311 | return AMDGPU_FW_LOAD_DIRECT; | ||
| 312 | default: | 312 | default: |
| 313 | DRM_ERROR("Unknown firmware load type\n"); | 313 | DRM_ERROR("Unknown firmware load type\n"); |
| 314 | } | 314 | } |
| @@ -322,6 +322,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, | |||
| 322 | { | 322 | { |
| 323 | const struct common_firmware_header *header = NULL; | 323 | const struct common_firmware_header *header = NULL; |
| 324 | const struct gfx_firmware_header_v1_0 *cp_hdr = NULL; | 324 | const struct gfx_firmware_header_v1_0 *cp_hdr = NULL; |
| 325 | const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL; | ||
| 325 | 326 | ||
| 326 | if (NULL == ucode->fw) | 327 | if (NULL == ucode->fw) |
| 327 | return 0; | 328 | return 0; |
| @@ -333,8 +334,8 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, | |||
| 333 | return 0; | 334 | return 0; |
| 334 | 335 | ||
| 335 | header = (const struct common_firmware_header *)ucode->fw->data; | 336 | header = (const struct common_firmware_header *)ucode->fw->data; |
| 336 | |||
| 337 | cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; | 337 | cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; |
| 338 | dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data; | ||
| 338 | 339 | ||
| 339 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP || | 340 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP || |
| 340 | (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 && | 341 | (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 && |
| @@ -343,7 +344,9 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, | |||
| 343 | ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT && | 344 | ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT && |
| 344 | ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL && | 345 | ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL && |
| 345 | ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM && | 346 | ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM && |
| 346 | ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM)) { | 347 | ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM && |
| 348 | ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM && | ||
| 349 | ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV)) { | ||
| 347 | ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); | 350 | ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); |
| 348 | 351 | ||
| 349 | memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + | 352 | memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + |
| @@ -365,6 +368,20 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, | |||
| 365 | le32_to_cpu(header->ucode_array_offset_bytes) + | 368 | le32_to_cpu(header->ucode_array_offset_bytes) + |
| 366 | le32_to_cpu(cp_hdr->jt_offset) * 4), | 369 | le32_to_cpu(cp_hdr->jt_offset) * 4), |
| 367 | ucode->ucode_size); | 370 | ucode->ucode_size); |
| 371 | } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_ERAM) { | ||
| 372 | ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - | ||
| 373 | le32_to_cpu(dmcu_hdr->intv_size_bytes); | ||
| 374 | |||
| 375 | memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + | ||
| 376 | le32_to_cpu(header->ucode_array_offset_bytes)), | ||
| 377 | ucode->ucode_size); | ||
| 378 | } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_INTV) { | ||
| 379 | ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes); | ||
| 380 | |||
| 381 | memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + | ||
| 382 | le32_to_cpu(header->ucode_array_offset_bytes) + | ||
| 383 | le32_to_cpu(dmcu_hdr->intv_offset_bytes)), | ||
| 384 | ucode->ucode_size); | ||
| 368 | } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) { | 385 | } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) { |
| 369 | ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes; | 386 | ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes; |
| 370 | memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl, | 387 | memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl, |
