Merge tag 'drm-next-2018-10-24' of git://anongit.freedesktop.org/drm/drm

Pull drm updates from Dave Airlie:
 "This is going to rebuild more than drm as it adds a new helper to
  list.h for doing bulk updates. Seemed like a reasonable addition to
  me.

  Otherwise the usual merge window stuff lots of i915 and amdgpu, not so
  much nouveau, and piles of everything else.

  Core:
   - Adds a new list.h helper for doing bulk list updates for TTM.
   - Don't leak fb address in smem_start to userspace (comes with EXPORT
     workaround for people using mali out of tree hacks)
   - udmabuf device to turn memfd regions into dma-buf
   - Per-plane blend mode property
   - ref/unref replacements with get/put
   - fbdev conflicting framebuffers code cleaned up
   - host-endian format variants
   - panel orientation quirk for Acer One 10

  bridge:
   - TI SN65DSI86 chip support

  vkms:
   - GEM support.
   - Cursor support

  amdgpu:
   - Merge amdkfd and amdgpu into one module
   - CEC over DP AUX support
   - Picasso APU support + VCN dynamic powergating
   - Raven2 APU support
   - Vega20 enablement + kfd support
   - ACP powergating improvements
   - ABGR/XBGR display support
   - VCN jpeg support
   - xGMI support
   - DC i2c/aux cleanup
   - Ycbcr 4:2:0 support
   - GPUVM improvements
   - Powerplay and powerplay endian fixes
   - Display underflow fixes

  vmwgfx:
   - Move vmwgfx specific TTM code to vmwgfx
   - Split out vmwgfx buffer/resource validation code
   - Atomic operation rework

  bochs:
   - use more helpers
   - format/byteorder improvements

  qxl:
   - use more helpers

  i915:
   - GGTT coherency getparam
   - Turn off resource streamer API
   - More Icelake enablement + DMC firmware
   - Full PPGTT for Ivybridge, Haswell and Valleyview
   - DDB distribution based on resolution
   - Limited range DP display support

  nouveau:
   - CEC over DP AUX support
   - Initial HDMI 2.0 support

  virtio-gpu:
   - vmap support for PRIME objects

  tegra:
   - Initial Tegra194 support
   - DMA/IOMMU integration fixes

  msm:
   - a6xx perf improvements + clock prefix
   - GPU preemption optimisations
   - a6xx devfreq support
   - cursor support

  rockchip:
   - PX30 support
   - rgb output interface support

  mediatek:
   - HDMI output support on mt2701 and mt7623

  rcar-du:
   - Interlaced modes on Gen3
   - LVDS on R8A77980
   - D3 and E3 SoC support

  hisilicon:
   - misc fixes

  mxsfb:
   - runtime pm support

  sun4i:
   - R40 TCON support
   - Allwinner A64 support
   - R40 HDMI support

  omapdrm:
   - Driver rework changing display pipeline ordering to use common code
   - DMM memory barrier and irq fixes
   - Errata workarounds

  exynos:
   - out-bridge support for LVDS bridge driver
   - Samsung 16x16 tiled format support
   - Plane alpha and pixel blend mode support

  tilcdc:
   - suspend/resume update

  mali-dp:
   - misc updates"

* tag 'drm-next-2018-10-24' of git://anongit.freedesktop.org/drm/drm: (1382 commits)
  firmware/dmc/icl: Add missing MODULE_FIRMWARE() for Icelake.
  drm/i915/icl: Fix signal_levels
  drm/i915/icl: Fix DDI/TC port clk_off bits
  drm/i915/icl: create function to identify combophy port
  drm/i915/gen9+: Fix initial readout for Y tiled framebuffers
  drm/i915: Large page offsets for pread/pwrite
  drm/i915/selftests: Disable shrinker across mmap-exhaustion
  drm/i915/dp: Link train Fallback on eDP only if fallback link BW can fit panel's native mode
  drm/i915: Fix intel_dp_mst_best_encoder()
  drm/i915: Skip vcpi allocation for MSTB ports that are gone
  drm/i915: Don't unset intel_connector->mst_port
  drm/i915: Only reset seqno if actually idle
  drm/i915: Use the correct crtc when sanitizing plane mapping
  drm/i915: Restore vblank interrupts earlier
  drm/i915: Check fb stride against plane max stride
  drm/amdgpu/vcn:Fix uninitialized symbol error
  drm: panel-orientation-quirks: Add quirk for Acer One 10 (S1003)
  drm/amd/amdgpu: Fix debugfs error handling
  drm/amdgpu: Update gc_9_0 golden settings.
  drm/amd/powerplay: update PPtable with DC BTC and Tvr SocLimit fields
  ...

1 files changed, 133 insertions, 91 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index fcf421263fd9..a44fc12ae1f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -47,6 +47,7 @@
 #include "amdgpu_object.h"
 #include "amdgpu_trace.h"
 #include "amdgpu_amdkfd.h"
+#include "amdgpu_sdma.h"
 #include "bif/bif_4_1_d.h"
 
 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
@@ -255,6 +256,13 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 
         abo = ttm_to_amdgpu_bo(bo);
         switch (bo->mem.mem_type) {
+        case AMDGPU_PL_GDS:
+        case AMDGPU_PL_GWS:
+        case AMDGPU_PL_OA:
+                placement->num_placement = 0;
+                placement->num_busy_placement = 0;
+                return;
+
         case TTM_PL_VRAM:
                 if (!adev->mman.buffer_funcs_enabled) {
                         /* Move to system memory */
@@ -282,6 +290,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
         case TTM_PL_TT:
         default:
                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
+                break;
         }
         *placement = abo->placement;
 }
@@ -344,7 +353,7 @@ static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 {
         uint64_t addr = 0;
 
-        if (mem->mem_type != TTM_PL_TT || amdgpu_gtt_mgr_has_gart_addr(mem)) {
+        if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
                 addr = mm_node->start << PAGE_SHIFT;
                 addr += bo->bdev->man[mem->mem_type].gpu_offset;
         }
@@ -432,8 +441,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
                 /* Map only what needs to be accessed. Map src to window 0 and
                  * dst to window 1
                  */
-                if (src->mem->mem_type == TTM_PL_TT &&
-                    !amdgpu_gtt_mgr_has_gart_addr(src->mem)) {
+                if (src->mem->start == AMDGPU_BO_INVALID_OFFSET) {
                         r = amdgpu_map_buffer(src->bo, src->mem,
                                         PFN_UP(cur_size + src_page_offset),
                                         src_node_start, 0, ring,
@@ -446,8 +454,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
                         from += src_page_offset;
                 }
 
-                if (dst->mem->mem_type == TTM_PL_TT &&
-                    !amdgpu_gtt_mgr_has_gart_addr(dst->mem)) {
+                if (dst->mem->start == AMDGPU_BO_INVALID_OFFSET) {
                         r = amdgpu_map_buffer(dst->bo, dst->mem,
                                         PFN_UP(cur_size + dst_page_offset),
                                         dst_node_start, 1, ring,
@@ -525,7 +532,11 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
         if (r)
                 goto error;
 
-        r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
+        /* Always block for VM page tables before committing the new location */
+        if (bo->type == ttm_bo_type_kernel)
+                r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
+        else
+                r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
         dma_fence_put(fence);
         return r;
 
@@ -676,6 +687,16 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
                 amdgpu_move_null(bo, new_mem);
                 return 0;
         }
+        if (old_mem->mem_type == AMDGPU_PL_GDS ||
+            old_mem->mem_type == AMDGPU_PL_GWS ||
+            old_mem->mem_type == AMDGPU_PL_OA ||
+            new_mem->mem_type == AMDGPU_PL_GDS ||
+            new_mem->mem_type == AMDGPU_PL_GWS ||
+            new_mem->mem_type == AMDGPU_PL_OA) {
+                /* Nothing to save here */
+                amdgpu_move_null(bo, new_mem);
+                return 0;
+        }
 
         if (!adev->mman.buffer_funcs_enabled)
                 goto memcpy;
@@ -1082,42 +1103,48 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
         struct ttm_mem_reg tmp;
         struct ttm_placement placement;
         struct ttm_place placements;
-        uint64_t flags;
+        uint64_t addr, flags;
         int r;
 
-        if (bo->mem.mem_type != TTM_PL_TT ||
-            amdgpu_gtt_mgr_has_gart_addr(&bo->mem))
+        if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
                 return 0;
 
-        /* allocate GTT space */
-        tmp = bo->mem;
-        tmp.mm_node = NULL;
-        placement.num_placement = 1;
-        placement.placement = &placements;
-        placement.num_busy_placement = 1;
-        placement.busy_placement = &placements;
-        placements.fpfn = 0;
-        placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
-        placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
-                TTM_PL_FLAG_TT;
+        addr = amdgpu_gmc_agp_addr(bo);
+        if (addr != AMDGPU_BO_INVALID_OFFSET) {
+                bo->mem.start = addr >> PAGE_SHIFT;
+        } else {
 
-        r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
-        if (unlikely(r))
-                return r;
+                /* allocate GART space */
+                tmp = bo->mem;
+                tmp.mm_node = NULL;
+                placement.num_placement = 1;
+                placement.placement = &placements;
+                placement.num_busy_placement = 1;
+                placement.busy_placement = &placements;
+                placements.fpfn = 0;
+                placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
+                placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
+                        TTM_PL_FLAG_TT;
+
+                r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
+                if (unlikely(r))
+                        return r;
 
-        /* compute PTE flags for this buffer object */
-        flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
+                /* compute PTE flags for this buffer object */
+                flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
 
-        /* Bind pages */
-        gtt->offset = (u64)tmp.start << PAGE_SHIFT;
-        r = amdgpu_ttm_gart_bind(adev, bo, flags);
-        if (unlikely(r)) {
-                ttm_bo_mem_put(bo, &tmp);
+                /* Bind pages */
+                gtt->offset = (u64)tmp.start << PAGE_SHIFT;
+                r = amdgpu_ttm_gart_bind(adev, bo, flags);
+                if (unlikely(r)) {
+                        ttm_bo_mem_put(bo, &tmp);