diff options
author | xinhui pan <xinhui.pan@amd.com> | 2019-03-11 02:12:40 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2019-03-19 16:36:51 -0400 |
commit | 5caf466a6e42beee88a707105975a1d2324b659c (patch) | |
tree | 8b13bb7e10211b6b547e3e9ef9a2498e6098b02e /drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | |
parent | 2b9505e3539e9869214485d4df997f9ed23ec3fe (diff) |
drm/amdgpu: add new member hw_supported
Currently, it is not clear how ras is supported. Both software and
hardware can set the supported. That is confusing.
Fix it by adding new member hw_supported.
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 42 |
1 files changed, 30 insertions, 12 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 750087535f00..74a65a61fd23 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | |||
@@ -469,7 +469,9 @@ static struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, | |||
469 | static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev, | 469 | static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev, |
470 | struct ras_common_if *head) | 470 | struct ras_common_if *head) |
471 | { | 471 | { |
472 | return amdgpu_ras_enable && (amdgpu_ras_mask & BIT(head->block)); | 472 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
473 | |||
474 | return con->hw_supported & BIT(head->block); | ||
473 | } | 475 | } |
474 | 476 | ||
475 | static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev, | 477 | static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev, |
@@ -490,6 +492,12 @@ static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |||
490 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | 492 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
491 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | 493 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); |
492 | 494 | ||
495 | /* If hardware does not support ras, then do not create obj. | ||
496 | * But if hardware support ras, we can create the obj. | ||
497 | * Ras framework checks con->hw_supported to see if it need do | ||
498 | * corresponding initialization. | ||
499 | * IP checks con->support to see if it need disable ras. | ||
500 | */ | ||
493 | if (!amdgpu_ras_is_feature_allowed(adev, head)) | 501 | if (!amdgpu_ras_is_feature_allowed(adev, head)) |
494 | return 0; | 502 | return 0; |
495 | if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) | 503 | if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) |
@@ -1334,27 +1342,36 @@ static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev) | |||
1334 | } | 1342 | } |
1335 | /* recovery end */ | 1343 | /* recovery end */ |
1336 | 1344 | ||
1337 | static uint32_t amdgpu_ras_check_supported(struct amdgpu_device *adev) | 1345 | /* |
1346 | * check hardware's ras ability which will be saved in hw_supported. | ||
1347 | * if hardware does not support ras, we can skip some ras initializtion and | ||
1348 | * forbid some ras operations from IP. | ||
1349 | * if software itself, say boot parameter, limit the ras ability. We still | ||
1350 | * need allow IP do some limited operations, like disable. In such case, | ||
1351 | * we have to initialize ras as normal. but need check if operation is | ||
1352 | * allowed or not in each function. | ||
1353 | */ | ||
1354 | static void amdgpu_ras_check_supported(struct amdgpu_device *adev, | ||
1355 | uint32_t *hw_supported, uint32_t *supported) | ||
1338 | { | 1356 | { |
1339 | uint32_t supported = 0; | 1357 | *hw_supported = 0; |
1358 | *supported = 0; | ||
1340 | 1359 | ||
1341 | if (amdgpu_ras_enable == 0 || | 1360 | if (amdgpu_sriov_vf(adev) || |
1342 | amdgpu_sriov_vf(adev) || | ||
1343 | adev->asic_type != CHIP_VEGA20) | 1361 | adev->asic_type != CHIP_VEGA20) |
1344 | return 0; | 1362 | return; |
1345 | 1363 | ||
1346 | if (amdgpu_atomfirmware_mem_ecc_supported(adev) || | 1364 | if (amdgpu_atomfirmware_mem_ecc_supported(adev) || |
1347 | amdgpu_atomfirmware_sram_ecc_supported(adev)) { | 1365 | amdgpu_atomfirmware_sram_ecc_supported(adev)) |
1348 | supported = AMDGPU_RAS_BLOCK_MASK; | 1366 | *hw_supported = AMDGPU_RAS_BLOCK_MASK; |
1349 | } | ||
1350 | 1367 | ||
1351 | return supported & amdgpu_ras_mask; | 1368 | *supported = amdgpu_ras_enable == 0 ? |
1369 | 0 : *hw_supported & amdgpu_ras_mask; | ||
1352 | } | 1370 | } |
1353 | 1371 | ||
1354 | int amdgpu_ras_init(struct amdgpu_device *adev) | 1372 | int amdgpu_ras_init(struct amdgpu_device *adev) |
1355 | { | 1373 | { |
1356 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | 1374 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
1357 | uint32_t supported = amdgpu_ras_check_supported(adev); | ||
1358 | 1375 | ||
1359 | if (con) | 1376 | if (con) |
1360 | return 0; | 1377 | return 0; |
@@ -1369,7 +1386,8 @@ int amdgpu_ras_init(struct amdgpu_device *adev) | |||
1369 | 1386 | ||
1370 | amdgpu_ras_set_context(adev, con); | 1387 | amdgpu_ras_set_context(adev, con); |
1371 | 1388 | ||
1372 | con->supported = supported; | 1389 | amdgpu_ras_check_supported(adev, &con->hw_supported, |
1390 | &con->supported); | ||
1373 | con->features = 0; | 1391 | con->features = 0; |
1374 | INIT_LIST_HEAD(&con->head); | 1392 | INIT_LIST_HEAD(&con->head); |
1375 | 1393 | ||