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authorxinhui pan <xinhui.pan@amd.com>2019-04-02 21:52:59 -0400
committerAlex Deucher <alexander.deucher@amd.com>2019-04-10 14:49:08 -0400
commit191051a1bef8257313d4bc4eafbf201e35e135e7 (patch)
tree980615609906c24779f7d0268d976caec430cc86 /drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
parent0e4f087ba2fe598a0add8b7cb2a3720e31ace1ed (diff)
drm/amdgpu: Make default ras error type to none
Unless IP has implemented its own ras, use ERROR_NONE as the default type. Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c24
1 files changed, 15 insertions, 9 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 469cb6477b8e..a0e34f62f110 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -558,11 +558,13 @@ static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
558 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 558 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
559 int ras_block_count = AMDGPU_RAS_BLOCK_COUNT; 559 int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
560 int i; 560 int i;
561 const enum amdgpu_ras_error_type default_ras_type =
562 AMDGPU_RAS_ERROR__NONE;
561 563
562 for (i = 0; i < ras_block_count; i++) { 564 for (i = 0; i < ras_block_count; i++) {
563 struct ras_common_if head = { 565 struct ras_common_if head = {
564 .block = i, 566 .block = i,
565 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 567 .type = default_ras_type,
566 .sub_block_index = 0, 568 .sub_block_index = 0,
567 }; 569 };
568 strcpy(head.name, ras_block_str(i)); 570 strcpy(head.name, ras_block_str(i));
@@ -1368,9 +1370,6 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
1368 1370
1369 amdgpu_ras_mask &= AMDGPU_RAS_BLOCK_MASK; 1371 amdgpu_ras_mask &= AMDGPU_RAS_BLOCK_MASK;
1370 1372
1371 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
1372 amdgpu_ras_enable_all_features(adev, 1);
1373
1374 if (amdgpu_ras_fs_init(adev)) 1373 if (amdgpu_ras_fs_init(adev))
1375 goto fs_out; 1374 goto fs_out;
1376 1375
@@ -1398,18 +1397,25 @@ void amdgpu_ras_post_init(struct amdgpu_device *adev)
1398 if (!con) 1397 if (!con)
1399 return; 1398 return;
1400 1399
1401 /* We enable ras on all hw_supported block, but as boot parameter might
1402 * disable some of them and one or more IP has not implemented yet.
1403 * So we disable them on behalf.
1404 */
1405 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { 1400 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
1401 /* Set up all other IPs which are not implemented. There is a
1402 * tricky thing that IP's actual ras error type should be
1403 * MULTI_UNCORRECTABLE, but as driver does not handle it, so
1404 * ERROR_NONE make sense anyway.
1405 */
1406 amdgpu_ras_enable_all_features(adev, 1);
1407
1408 /* We enable ras on all hw_supported block, but as boot
1409 * parameter might disable some of them and one or more IP has
1410 * not implemented yet. So we disable them on behalf.
1411 */
1406 list_for_each_entry_safe(obj, tmp, &con->head, node) { 1412 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1407 if (!amdgpu_ras_is_supported(adev, obj->head.block)) { 1413 if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
1408 amdgpu_ras_feature_enable(adev, &obj->head, 0); 1414 amdgpu_ras_feature_enable(adev, &obj->head, 0);
1409 /* there should be no any reference. */ 1415 /* there should be no any reference. */
1410 WARN_ON(alive_obj(obj)); 1416 WARN_ON(alive_obj(obj));
1411 } 1417 }
1412 }; 1418 }
1413 } 1419 }
1414} 1420}
1415 1421