aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2018-10-28 20:49:53 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2018-10-28 20:49:53 -0400
commit53b3b6bbfde6aae8d1ededc86ad4e0e1e00eb5f8 (patch)
treeb29473f21270aefd113b298c9402be8b4b3c91b4 /drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
parent746bb4ed6d626f3f9e431a7f9b20504538e62ded (diff)
parentf2bfc71aee75feff33ca659322b72ffeed5a243d (diff)
Merge tag 'drm-next-2018-10-24' of git://anongit.freedesktop.org/drm/drm
Pull drm updates from Dave Airlie: "This is going to rebuild more than drm as it adds a new helper to list.h for doing bulk updates. Seemed like a reasonable addition to me. Otherwise the usual merge window stuff lots of i915 and amdgpu, not so much nouveau, and piles of everything else. Core: - Adds a new list.h helper for doing bulk list updates for TTM. - Don't leak fb address in smem_start to userspace (comes with EXPORT workaround for people using mali out of tree hacks) - udmabuf device to turn memfd regions into dma-buf - Per-plane blend mode property - ref/unref replacements with get/put - fbdev conflicting framebuffers code cleaned up - host-endian format variants - panel orientation quirk for Acer One 10 bridge: - TI SN65DSI86 chip support vkms: - GEM support. - Cursor support amdgpu: - Merge amdkfd and amdgpu into one module - CEC over DP AUX support - Picasso APU support + VCN dynamic powergating - Raven2 APU support - Vega20 enablement + kfd support - ACP powergating improvements - ABGR/XBGR display support - VCN jpeg support - xGMI support - DC i2c/aux cleanup - Ycbcr 4:2:0 support - GPUVM improvements - Powerplay and powerplay endian fixes - Display underflow fixes vmwgfx: - Move vmwgfx specific TTM code to vmwgfx - Split out vmwgfx buffer/resource validation code - Atomic operation rework bochs: - use more helpers - format/byteorder improvements qxl: - use more helpers i915: - GGTT coherency getparam - Turn off resource streamer API - More Icelake enablement + DMC firmware - Full PPGTT for Ivybridge, Haswell and Valleyview - DDB distribution based on resolution - Limited range DP display support nouveau: - CEC over DP AUX support - Initial HDMI 2.0 support virtio-gpu: - vmap support for PRIME objects tegra: - Initial Tegra194 support - DMA/IOMMU integration fixes msm: - a6xx perf improvements + clock prefix - GPU preemption optimisations - a6xx devfreq support - cursor support rockchip: - PX30 support - rgb output interface support mediatek: - HDMI output support on mt2701 and mt7623 rcar-du: - Interlaced modes on Gen3 - LVDS on R8A77980 - D3 and E3 SoC support hisilicon: - misc fixes mxsfb: - runtime pm support sun4i: - R40 TCON support - Allwinner A64 support - R40 HDMI support omapdrm: - Driver rework changing display pipeline ordering to use common code - DMM memory barrier and irq fixes - Errata workarounds exynos: - out-bridge support for LVDS bridge driver - Samsung 16x16 tiled format support - Plane alpha and pixel blend mode support tilcdc: - suspend/resume update mali-dp: - misc updates" * tag 'drm-next-2018-10-24' of git://anongit.freedesktop.org/drm/drm: (1382 commits) firmware/dmc/icl: Add missing MODULE_FIRMWARE() for Icelake. drm/i915/icl: Fix signal_levels drm/i915/icl: Fix DDI/TC port clk_off bits drm/i915/icl: create function to identify combophy port drm/i915/gen9+: Fix initial readout for Y tiled framebuffers drm/i915: Large page offsets for pread/pwrite drm/i915/selftests: Disable shrinker across mmap-exhaustion drm/i915/dp: Link train Fallback on eDP only if fallback link BW can fit panel's native mode drm/i915: Fix intel_dp_mst_best_encoder() drm/i915: Skip vcpi allocation for MSTB ports that are gone drm/i915: Don't unset intel_connector->mst_port drm/i915: Only reset seqno if actually idle drm/i915: Use the correct crtc when sanitizing plane mapping drm/i915: Restore vblank interrupts earlier drm/i915: Check fb stride against plane max stride drm/amdgpu/vcn:Fix uninitialized symbol error drm: panel-orientation-quirks: Add quirk for Acer One 10 (S1003) drm/amd/amdgpu: Fix debugfs error handling drm/amdgpu: Update gc_9_0 golden settings. drm/amd/powerplay: update PPtable with DC BTC and Tvr SocLimit fields ...
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c316
1 files changed, 0 insertions, 316 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
deleted file mode 100644
index a172bba32b45..000000000000
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
+++ /dev/null
@@ -1,316 +0,0 @@
1/*
2 * Copyright 2017 Valve Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Andres Rodriguez
23 */
24
25#include "amdgpu.h"
26#include "amdgpu_ring.h"
27
28static int amdgpu_queue_mapper_init(struct amdgpu_queue_mapper *mapper,
29 int hw_ip)
30{
31 if (!mapper)
32 return -EINVAL;
33
34 if (hw_ip > AMDGPU_MAX_IP_NUM)
35 return -EINVAL;
36
37 mapper->hw_ip = hw_ip;
38 mutex_init(&mapper->lock);
39
40 memset(mapper->queue_map, 0, sizeof(mapper->queue_map));
41
42 return 0;
43}
44
45static struct amdgpu_ring *amdgpu_get_cached_map(struct amdgpu_queue_mapper *mapper,
46 int ring)
47{
48 return mapper->queue_map[ring];
49}
50
51static int amdgpu_update_cached_map(struct amdgpu_queue_mapper *mapper,
52 int ring, struct amdgpu_ring *pring)
53{
54 if (WARN_ON(mapper->queue_map[ring])) {
55 DRM_ERROR("Un-expected ring re-map\n");
56 return -EINVAL;
57 }
58
59 mapper->queue_map[ring] = pring;
60
61 return 0;
62}
63
64static int amdgpu_identity_map(struct amdgpu_device *adev,
65 struct amdgpu_queue_mapper *mapper,
66 u32 ring,
67 struct amdgpu_ring **out_ring)
68{
69 switch (mapper->hw_ip) {
70 case AMDGPU_HW_IP_GFX:
71 *out_ring = &adev->gfx.gfx_ring[ring];
72 break;
73 case AMDGPU_HW_IP_COMPUTE:
74 *out_ring = &adev->gfx.compute_ring[ring];
75 break;
76 case AMDGPU_HW_IP_DMA:
77 *out_ring = &adev->sdma.instance[ring].ring;
78 break;
79 case AMDGPU_HW_IP_UVD:
80 *out_ring = &adev->uvd.inst[0].ring;
81 break;
82 case AMDGPU_HW_IP_VCE:
83 *out_ring = &adev->vce.ring[ring];
84 break;
85 case AMDGPU_HW_IP_UVD_ENC:
86 *out_ring = &adev->uvd.inst[0].ring_enc[ring];
87 break;
88 case AMDGPU_HW_IP_VCN_DEC:
89 *out_ring = &adev->vcn.ring_dec;
90 break;
91 case AMDGPU_HW_IP_VCN_ENC:
92 *out_ring = &adev->vcn.ring_enc[ring];
93 break;
94 case AMDGPU_HW_IP_VCN_JPEG:
95 *out_ring = &adev->vcn.ring_jpeg;
96 break;
97 default:
98 *out_ring = NULL;
99 DRM_ERROR("unknown HW IP type: %d\n", mapper->hw_ip);
100 return -EINVAL;
101 }
102
103 return amdgpu_update_cached_map(mapper, ring, *out_ring);
104}
105
106static enum amdgpu_ring_type amdgpu_hw_ip_to_ring_type(int hw_ip)
107{
108 switch (hw_ip) {
109 case AMDGPU_HW_IP_GFX:
110 return AMDGPU_RING_TYPE_GFX;
111 case AMDGPU_HW_IP_COMPUTE:
112 return AMDGPU_RING_TYPE_COMPUTE;
113 case AMDGPU_HW_IP_DMA:
114 return AMDGPU_RING_TYPE_SDMA;
115 case AMDGPU_HW_IP_UVD:
116 return AMDGPU_RING_TYPE_UVD;
117 case AMDGPU_HW_IP_VCE:
118 return AMDGPU_RING_TYPE_VCE;
119 default:
120 DRM_ERROR("Invalid HW IP specified %d\n", hw_ip);
121 return -1;
122 }
123}
124
125static int amdgpu_lru_map(struct amdgpu_device *adev,
126 struct amdgpu_queue_mapper *mapper,
127 u32 user_ring, bool lru_pipe_order,
128 struct amdgpu_ring **out_ring)
129{
130 int r, i, j;
131 int ring_type = amdgpu_hw_ip_to_ring_type(mapper->hw_ip);
132 int ring_blacklist[AMDGPU_MAX_RINGS];
133 struct amdgpu_ring *ring;
134
135 /* 0 is a valid ring index, so initialize to -1 */
136 memset(ring_blacklist, 0xff, sizeof(ring_blacklist));
137
138 for (i = 0, j = 0; i < AMDGPU_MAX_RINGS; i++) {
139 ring = mapper->queue_map[i];
140 if (ring)
141 ring_blacklist[j++] = ring->idx;
142 }
143
144 r = amdgpu_ring_lru_get(adev, ring_type, ring_blacklist,
145 j, lru_pipe_order, out_ring);
146 if (r)
147 return r;
148
149 return amdgpu_update_cached_map(mapper, user_ring, *out_ring);
150}
151
152/**
153 * amdgpu_queue_mgr_init - init an amdgpu_queue_mgr struct
154 *
155 * @adev: amdgpu_device pointer
156 * @mgr: amdgpu_queue_mgr structure holding queue information
157 *
158 * Initialize the the selected @mgr (all asics).
159 *
160 * Returns 0 on success, error on failure.
161 */
162int amdgpu_queue_mgr_init(struct amdgpu_device *adev,
163 struct amdgpu_queue_mgr *mgr)
164{
165 int i, r;
166
167 if (!adev || !mgr)
168 return -EINVAL;
169
170 memset(mgr, 0, sizeof(*mgr));
171
172 for (i = 0; i < AMDGPU_MAX_IP_NUM; ++i) {
173 r = amdgpu_queue_mapper_init(&mgr->mapper[i], i);
174 if (r)
175 return r;
176 }
177
178 return 0;