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authorJames Zhu <James.Zhu@amd.com>2018-04-23 21:00:58 -0400
committerAlex Deucher <alexander.deucher@amd.com>2018-05-18 17:08:14 -0400
commit04305acb9f7fc9978ed7a14bf965802c45ea9682 (patch)
tree8d448ca12b305412e28db4e351a65c35918756d0 /drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
parentb53a6ebcc55971169e56982fd9131d1a6969a053 (diff)
drm/amdgpu/vg20:Enable 2nd instance queue maping for uvd 7.2
Enable 2nd instance uvd queue maping for uvd 7.2. For user, only one UVD instance presents. there is two rings for uvd decode, and 4 rings for uvd encode. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c14
1 files changed, 10 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
index 2458d385e55a..8af16e81c7d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
@@ -66,6 +66,8 @@ static int amdgpu_identity_map(struct amdgpu_device *adev,
66 u32 ring, 66 u32 ring,
67 struct amdgpu_ring **out_ring) 67 struct amdgpu_ring **out_ring)
68{ 68{
69 u32 instance;
70
69 switch (mapper->hw_ip) { 71 switch (mapper->hw_ip) {
70 case AMDGPU_HW_IP_GFX: 72 case AMDGPU_HW_IP_GFX:
71 *out_ring = &adev->gfx.gfx_ring[ring]; 73 *out_ring = &adev->gfx.gfx_ring[ring];
@@ -77,13 +79,16 @@ static int amdgpu_identity_map(struct amdgpu_device *adev,
77 *out_ring = &adev->sdma.instance[ring].ring; 79 *out_ring = &adev->sdma.instance[ring].ring;
78 break; 80 break;
79 case AMDGPU_HW_IP_UVD: 81 case AMDGPU_HW_IP_UVD:
80 *out_ring = &adev->uvd.inst->ring; 82 instance = ring;
83 *out_ring = &adev->uvd.inst[instance].ring;
81 break; 84 break;
82 case AMDGPU_HW_IP_VCE: 85 case AMDGPU_HW_IP_VCE:
83 *out_ring = &adev->vce.ring[ring]; 86 *out_ring = &adev->vce.ring[ring];
84 break; 87 break;
85 case AMDGPU_HW_IP_UVD_ENC: 88 case AMDGPU_HW_IP_UVD_ENC:
86 *out_ring = &adev->uvd.inst->ring_enc[ring]; 89 instance = ring / adev->uvd.num_enc_rings;
90 *out_ring =
91 &adev->uvd.inst[instance].ring_enc[ring%adev->uvd.num_enc_rings];
87 break; 92 break;
88 case AMDGPU_HW_IP_VCN_DEC: 93 case AMDGPU_HW_IP_VCN_DEC:
89 *out_ring = &adev->vcn.ring_dec; 94 *out_ring = &adev->vcn.ring_dec;
@@ -240,13 +245,14 @@ int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
240 ip_num_rings = adev->sdma.num_instances; 245 ip_num_rings = adev->sdma.num_instances;
241 break; 246 break;
242 case AMDGPU_HW_IP_UVD: 247 case AMDGPU_HW_IP_UVD:
243 ip_num_rings = 1; 248 ip_num_rings = adev->uvd.num_uvd_inst;
244 break; 249 break;
245 case AMDGPU_HW_IP_VCE: 250 case AMDGPU_HW_IP_VCE:
246 ip_num_rings = adev->vce.num_rings; 251 ip_num_rings = adev->vce.num_rings;
247 break; 252 break;
248 case AMDGPU_HW_IP_UVD_ENC: 253 case AMDGPU_HW_IP_UVD_ENC:
249 ip_num_rings = adev->uvd.num_enc_rings; 254 ip_num_rings =
255 adev->uvd.num_enc_rings * adev->uvd.num_uvd_inst;
250 break; 256 break;
251 case AMDGPU_HW_IP_VCN_DEC: 257 case AMDGPU_HW_IP_VCN_DEC:
252 ip_num_rings = 1; 258 ip_num_rings = 1;