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authorMario Kleiner <mario.kleiner.de@gmail.com>2016-11-08 20:25:15 -0500
committerAlex Deucher <alexander.deucher@amd.com>2016-11-11 10:20:04 -0500
commit8e94a46c1770884166b31adc99eba7da65a446a7 (patch)
tree5d4e3e66977544e85dc2fb499a32a243cafbfaa4 /drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
parente2384535a623ed51151d1bbed5263b9f8a87a74d (diff)
drm/amdgpu: Attach exclusive fence to prime exported bo's. (v5)
External clients which import our bo's wait only for exclusive dmabuf-fences, not on shared ones, ditto for bo's which we import from external providers and write to. Therefore attach exclusive fences on prime shared buffers if our exported buffer gets imported by an external client, or if we import a buffer from an external exporter. See discussion in thread: https://lists.freedesktop.org/archives/dri-devel/2016-October/122370.html Prime export tested on Intel iGPU + AMD Tonga dGPU as DRI3/Present Prime render offload, and with the Tonga standalone as primary gpu. v2: Add a wait for all shared fences before prime export, as suggested by Christian Koenig. v3: - Mark buffer prime_exported in amdgpu_gem_prime_pin, so we only use the exclusive fence when exporting a bo to external clients like a separate iGPU, but not when exporting/importing from/to ourselves as part of regular DRI3 fd passing. - Propagate failure of reservation_object_wait_rcu back to caller. v4: - Switch to a prime_shared_count counter instead of a flag, which gets in/decremented on prime_pin/unpin, so we can switch back to shared fences if all clients detach from our exported bo. - Also switch to exclusive fence for prime imported bo's. v5: - Drop lret, instead use int ret -> long ret, as proposed by Christian. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95472 Tested-by: Mike Lothian <mike@fireburn.co.uk> (v1) Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Reviewed-by: Christian König <christian.koenig@amd.com>. Cc: Christian König <christian.koenig@amd.com> Cc: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c20
1 files changed, 19 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
index 7700dc22f243..3826d5aea0a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
@@ -74,20 +74,36 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
74 if (ret) 74 if (ret)
75 return ERR_PTR(ret); 75 return ERR_PTR(ret);
76 76
77 bo->prime_shared_count = 1;
77 return &bo->gem_base; 78 return &bo->gem_base;
78} 79}
79 80
80int amdgpu_gem_prime_pin(struct drm_gem_object *obj) 81int amdgpu_gem_prime_pin(struct drm_gem_object *obj)
81{ 82{
82 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 83 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
83 int ret = 0; 84 long ret = 0;
84 85
85 ret = amdgpu_bo_reserve(bo, false); 86 ret = amdgpu_bo_reserve(bo, false);
86 if (unlikely(ret != 0)) 87 if (unlikely(ret != 0))
87 return ret; 88 return ret;
88 89
90 /*
91 * Wait for all shared fences to complete before we switch to future
92 * use of exclusive fence on this prime shared bo.
93 */
94 ret = reservation_object_wait_timeout_rcu(bo->tbo.resv, true, false,
95 MAX_SCHEDULE_TIMEOUT);
96 if (unlikely(ret < 0)) {
97 DRM_DEBUG_PRIME("Fence wait failed: %li\n", ret);
98 amdgpu_bo_unreserve(bo);
99 return ret;
100 }
101
89 /* pin buffer into GTT */ 102 /* pin buffer into GTT */
90 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT, NULL); 103 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT, NULL);
104 if (likely(ret == 0))
105 bo->prime_shared_count++;
106
91 amdgpu_bo_unreserve(bo); 107 amdgpu_bo_unreserve(bo);
92 return ret; 108 return ret;
93} 109}
@@ -102,6 +118,8 @@ void amdgpu_gem_prime_unpin(struct drm_gem_object *obj)
102 return; 118 return;
103 119
104 amdgpu_bo_unpin(bo); 120 amdgpu_bo_unpin(bo);
121 if (bo->prime_shared_count)
122 bo->prime_shared_count--;
105 amdgpu_bo_unreserve(bo); 123 amdgpu_bo_unreserve(bo);
106} 124}
107 125