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authorEvan Quan <evan.quan@amd.com>2019-01-14 01:45:47 -0500
committerAlex Deucher <alexander.deucher@amd.com>2019-01-25 16:15:34 -0500
commitd7337ca2640cde21ff178bd78f01d94cd5ea2e08 (patch)
tree22cb297fb192f51f127e3e51f34ef3e0146968fe /drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
parent7ca881a8651bdeffd99ba8e0010160f9bf60673e (diff)
drm/amd/powerplay: support retrieving and adjusting SOC clock power levels V2
User can use "pp_dpm_socclk" to retrieve and adjust SOC clock power levels. V2: expose this interface for Vega10 and later ASICs only Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c54
1 files changed, 52 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index f21f294e6735..4bdb1d082bea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -680,11 +680,13 @@ static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
680} 680}
681 681
682/** 682/**
683 * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie 683 * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_pcie
684 * 684 *
685 * The amdgpu driver provides a sysfs API for adjusting what power levels 685 * The amdgpu driver provides a sysfs API for adjusting what power levels
686 * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk, 686 * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk,
687 * and pp_dpm_pcie are used for this. 687 * pp_dpm_socclk and pp_dpm_pcie are used for this.
688 *
689 * pp_dpm_socclk interface is only available for Vega10 and later ASICs.
688 * 690 *
689 * Reading back the files will show you the available power levels within 691 * Reading back the files will show you the available power levels within
690 * the power state and the clock information for those levels. 692 * the power state and the clock information for those levels.
@@ -804,6 +806,42 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
804 return count; 806 return count;
805} 807}
806 808
809static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
810 struct device_attribute *attr,
811 char *buf)
812{
813 struct drm_device *ddev = dev_get_drvdata(dev);
814 struct amdgpu_device *adev = ddev->dev_private;
815
816 if (adev->powerplay.pp_funcs->print_clock_levels)
817 return amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf);
818 else
819 return snprintf(buf, PAGE_SIZE, "\n");
820}
821
822static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
823 struct device_attribute *attr,
824 const char *buf,
825 size_t count)
826{
827 struct drm_device *ddev = dev_get_drvdata(dev);
828 struct amdgpu_device *adev = ddev->dev_private;
829 int ret;
830 uint32_t mask = 0;
831
832 ret = amdgpu_read_mask(buf, count, &mask);
833 if (ret)
834 return ret;
835
836 if (adev->powerplay.pp_funcs->force_clock_level)
837 ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
838
839 if (ret)
840 return -EINVAL;
841
842 return count;
843}
844
807static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev, 845static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
808 struct device_attribute *attr, 846 struct device_attribute *attr,
809 char *buf) 847 char *buf)
@@ -1087,6 +1125,9 @@ static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
1087static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR, 1125static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
1088 amdgpu_get_pp_dpm_mclk, 1126 amdgpu_get_pp_dpm_mclk,
1089 amdgpu_set_pp_dpm_mclk); 1127 amdgpu_set_pp_dpm_mclk);
1128static DEVICE_ATTR(pp_dpm_socclk, S_IRUGO | S_IWUSR,
1129 amdgpu_get_pp_dpm_socclk,
1130 amdgpu_set_pp_dpm_socclk);
1090static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR, 1131static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
1091 amdgpu_get_pp_dpm_pcie, 1132 amdgpu_get_pp_dpm_pcie,
1092 amdgpu_set_pp_dpm_pcie); 1133 amdgpu_set_pp_dpm_pcie);
@@ -2246,6 +2287,13 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
2246 DRM_ERROR("failed to create device file pp_dpm_mclk\n"); 2287 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
2247 return ret; 2288 return ret;
2248 } 2289 }
2290 if (adev->asic_type >= CHIP_VEGA10) {
2291 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_socclk);
2292 if (ret) {
2293 DRM_ERROR("failed to create device file pp_dpm_socclk\n");
2294 return ret;
2295 }
2296 }
2249 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie); 2297 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
2250 if (ret) { 2298 if (ret) {
2251 DRM_ERROR("failed to create device file pp_dpm_pcie\n"); 2299 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
@@ -2333,6 +2381,8 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
2333 2381
2334 device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk); 2382 device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
2335 device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk); 2383 device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
2384 if (adev->asic_type >= CHIP_VEGA10)
2385 device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);
2336 device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie); 2386 device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
2337 device_remove_file(adev->dev, &dev_attr_pp_sclk_od); 2387 device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
2338 device_remove_file(adev->dev, &dev_attr_pp_mclk_od); 2388 device_remove_file(adev->dev, &dev_attr_pp_mclk_od);