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authorLikun Gao <Likun.Gao@amd.com>2019-01-24 06:53:40 -0500
committerAlex Deucher <alexander.deucher@amd.com>2019-03-19 16:04:01 -0400
commitbc0fcffd36baa1cbbf2a6e951e4f1acad3aa8c90 (patch)
treeadb5efa55fc38f2fb84d5692f3411c7e1f2e1879 /drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
parent72e91f37a81768c81aa7ac78169f5a3259c621ac (diff)
drm/amd/powerplay: Unify smu handle task function (v2)
Unify power stade adjust function into smu_handle_task by the judgment of task_id. Move functions which have no relationship with smu version into the file of amdgpu_smu. Modified the function of smu_display_config_changed into two part. Unify some similiar function. v2: Correct the operation of upload dpm level when force dpm limit value. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c46
1 files changed, 28 insertions, 18 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index b83981284a7c..47d2ba528a0f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -2608,28 +2608,38 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
2608 amdgpu_fence_wait_empty(ring); 2608 amdgpu_fence_wait_empty(ring);
2609 } 2609 }
2610 2610
2611 if (adev->powerplay.pp_funcs->dispatch_tasks) { 2611 if (is_support_sw_smu(adev)) {
2612 if (!amdgpu_device_has_dc_support(adev)) { 2612 struct smu_context *smu = &adev->smu;
2613 struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
2614 mutex_lock(&(smu->mutex));
2615 smu_handle_task(&adev->smu,
2616 smu_dpm->dpm_level,
2617 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE);
2618 mutex_unlock(&(smu->mutex));
2619 } else {
2620 if (adev->powerplay.pp_funcs->dispatch_tasks) {
2621 if (!amdgpu_device_has_dc_support(adev)) {
2622 mutex_lock(&adev->pm.mutex);
2623 amdgpu_dpm_get_active_displays(adev);
2624 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
2625 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
2626 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
2627 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
2628 if (adev->pm.pm_display_cfg.vrefresh > 120)
2629 adev->pm.pm_display_cfg.min_vblank_time = 0;
2630 if (adev->powerplay.pp_funcs->display_configuration_change)
2631 adev->powerplay.pp_funcs->display_configuration_change(
2632 adev->powerplay.pp_handle,
2633 &adev->pm.pm_display_cfg);
2634 mutex_unlock(&adev->pm.mutex);
2635 }
2636 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
2637 } else {
2613 mutex_lock(&adev->pm.mutex); 2638 mutex_lock(&adev->pm.mutex);
2614 amdgpu_dpm_get_active_displays(adev); 2639 amdgpu_dpm_get_active_displays(adev);
2615 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count; 2640 amdgpu_dpm_change_power_state_locked(adev);
2616 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
2617 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
2618 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
2619 if (adev->pm.pm_display_cfg.vrefresh > 120)
2620 adev->pm.pm_display_cfg.min_vblank_time = 0;
2621 if (adev->powerplay.pp_funcs->display_configuration_change)
2622 adev->powerplay.pp_funcs->display_configuration_change(
2623 adev->powerplay.pp_handle,
2624 &adev->pm.pm_display_cfg);
2625 mutex_unlock(&adev->pm.mutex); 2641 mutex_unlock(&adev->pm.mutex);
2626 } 2642 }
2627 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
2628 } else {
2629 mutex_lock(&adev->pm.mutex);
2630 amdgpu_dpm_get_active_displays(adev);
2631 amdgpu_dpm_change_power_state_locked(adev);
2632 mutex_unlock(&adev->pm.mutex);
2633 } 2643 }
2634} 2644}
2635 2645