drm/amd/pp: Unify powergate_uvd/vce/mmhub to set_powergating_by_smu

Some HW ip blocks need call SMU to enter/leave power gate state.
So export common set_powergating_by_smu interface.

1. keep consistent with set_clockgating_by_smu
2. scales easily to powergate other ip(gfx) if necessary

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 4 insertions, 4 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index fdb399821915..a003fd881a89 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1729,10 +1729,10 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
 
 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
 {
-        if (adev->powerplay.pp_funcs->powergate_uvd) {
+        if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
                 /* enable/disable UVD */
                 mutex_lock(&adev->pm.mutex);
-                amdgpu_dpm_powergate_uvd(adev, !enable);
+                amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
                 mutex_unlock(&adev->pm.mutex);
         } else {
                 if (enable) {
@@ -1751,10 +1751,10 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
 
 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
 {
-        if (adev->powerplay.pp_funcs->powergate_vce) {
+        if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
                 /* enable/disable VCE */
                 mutex_lock(&adev->pm.mutex);
-                amdgpu_dpm_powergate_vce(adev, !enable);
+                amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
                 mutex_unlock(&adev->pm.mutex);
         } else {
                 if (enable) {