drm/amd/powerplay: add dpm force multiple levels on cz/tonga/fiji/polaris (v2)

Allows you to force multiple levels rather than just one via the new
sysfs interrface.

v2: squash in:
drm/amd/powerplay: ensure clock level set by user is valid.
From Rex.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 36 insertions, 15 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 6d44d4a64698..589b36e8c5cf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -362,16 +362,23 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
         struct amdgpu_device *adev = ddev->dev_private;
         int ret;
         long level;
+        uint32_t i, mask = 0;
+        char sub_str[2];
 
-        ret = kstrtol(buf, 0, &level);
+        for (i = 0; i < strlen(buf) - 1; i++) {
+                sub_str[0] = *(buf + i);
+                sub_str[1] = '\0';
+                ret = kstrtol(sub_str, 0, &level);
 
-        if (ret) {
-                count = -EINVAL;
-                goto fail;
+                if (ret) {
+                        count = -EINVAL;
+                        goto fail;
+                }
+                mask |= 1 << level;
         }
 
         if (adev->pp_enabled)
-                amdgpu_dpm_force_clock_level(adev, PP_SCLK, level);
+                amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 fail:
         return count;
 }
@@ -399,16 +406,23 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
         struct amdgpu_device *adev = ddev->dev_private;
         int ret;
         long level;
+        uint32_t i, mask = 0;
+        char sub_str[2];
 
-        ret = kstrtol(buf, 0, &level);
+        for (i = 0; i < strlen(buf) - 1; i++) {
+                sub_str[0] = *(buf + i);
+                sub_str[1] = '\0';
+                ret = kstrtol(sub_str, 0, &level);
 
-        if (ret) {
-                count = -EINVAL;
-                goto fail;
+                if (ret) {
+                        count = -EINVAL;
+                        goto fail;
+                }
+                mask |= 1 << level;
         }
 
         if (adev->pp_enabled)
-                amdgpu_dpm_force_clock_level(adev, PP_MCLK, level);
+                amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 fail:
         return count;
 }
@@ -436,16 +450,23 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
         struct amdgpu_device *adev = ddev->dev_private;
         int ret;
         long level;
+        uint32_t i, mask = 0;
+        char sub_str[2];
 
-        ret = kstrtol(buf, 0, &level);
+        for (i = 0; i < strlen(buf) - 1; i++) {
+                sub_str[0] = *(buf + i);
+                sub_str[1] = '\0';
+                ret = kstrtol(sub_str, 0, &level);
 
-        if (ret) {
-                count = -EINVAL;
-                goto fail;
+                if (ret) {
+                        count = -EINVAL;
+                        goto fail;
+                }
+                mask |= 1 << level;
         }
 
         if (adev->pp_enabled)
-                amdgpu_dpm_force_clock_level(adev, PP_PCIE, level);
+                amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
 fail:
         return count;
 }