diff options
author | Likun Gao <Likun.Gao@amd.com> | 2019-02-20 00:42:55 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2019-03-19 16:04:02 -0400 |
commit | 4b77faaf8c3be77a3f435333d62905989f0a3a40 (patch) | |
tree | 5b05ecf7115e1bf162999ac881ac03cb388d00e6 /drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | |
parent | 0967610142275c3aa1b73d923505cb8e73916af5 (diff) |
drm/amd/powerplay: support sysfs to set socclk, fclk, dcefclk
Add sys interface to set socclk, fclk and dcefclk for smu.
Add feature_mask parameter for smu_upload_dpm_level as socclk, fclk and
dcefclk have dependency, without feature_mask to point out specific clk
will make it fail to set some clk.
Fix the function of smu_unforce_dpm_levels.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Gui Chengming <Jack.Gui@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index 99309153fb9e..e05108ed1a2b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | |||
@@ -928,7 +928,9 @@ static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev, | |||
928 | if (ret) | 928 | if (ret) |
929 | return ret; | 929 | return ret; |
930 | 930 | ||
931 | if (adev->powerplay.pp_funcs->force_clock_level) | 931 | if (is_support_sw_smu(adev)) |
932 | ret = smu_force_clk_levels(&adev->smu, PP_SOCCLK, mask); | ||
933 | else if (adev->powerplay.pp_funcs->force_clock_level) | ||
932 | ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask); | 934 | ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask); |
933 | 935 | ||
934 | if (ret) | 936 | if (ret) |
@@ -966,7 +968,9 @@ static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev, | |||
966 | if (ret) | 968 | if (ret) |
967 | return ret; | 969 | return ret; |
968 | 970 | ||
969 | if (adev->powerplay.pp_funcs->force_clock_level) | 971 | if (is_support_sw_smu(adev)) |
972 | ret = smu_force_clk_levels(&adev->smu, PP_FCLK, mask); | ||
973 | else if (adev->powerplay.pp_funcs->force_clock_level) | ||
970 | ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask); | 974 | ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask); |
971 | 975 | ||
972 | if (ret) | 976 | if (ret) |
@@ -1004,7 +1008,9 @@ static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev, | |||
1004 | if (ret) | 1008 | if (ret) |
1005 | return ret; | 1009 | return ret; |
1006 | 1010 | ||
1007 | if (adev->powerplay.pp_funcs->force_clock_level) | 1011 | if (is_support_sw_smu(adev)) |
1012 | ret = smu_force_clk_levels(&adev->smu, PP_DCEFCLK, mask); | ||
1013 | else if (adev->powerplay.pp_funcs->force_clock_level) | ||
1008 | ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask); | 1014 | ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask); |
1009 | 1015 | ||
1010 | if (ret) | 1016 | if (ret) |