drm/amdgpu: remove VI hw bug workaround v3

The workaround simply doesn't work because VM mappings
are controlled by userspace not the kernel.

Additional to that this is just a performance problem
which happens if you have holes in your VM mapping.

v2: adjust virtual addr alignment as well.
v3: fix trivial warning

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Monk Liu  <monk.liu@amd.com> (v1)
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> (v2)

1 files changed, 0 insertions, 12 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 87d67f8c85c9..f1f1b6796669 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -223,18 +223,6 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
         size_t acc_size;
         int r;
 
-        /* VI has a hw bug where VM PTEs have to be allocated in groups of 8.
-         * do this as a temporary workaround
-         */
-        if (!(domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) {
-                if ((adev->asic_type >= CHIP_TOPAZ) && (adev->asic_type != CHIP_FIJI)) {
-                        if (byte_align & 0x7fff)
-                                byte_align = ALIGN(byte_align, 0x8000);
-                        if (size & 0x7fff)
-                                size = ALIGN(size, 0x8000);
-                }
-        }
-
         page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
         size = ALIGN(size, PAGE_SIZE);