Merge tag 'drm-fixes-2018-06-22' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
 "Just run of the mill fixes,

  core:
   - regression fix in device unplug

  qxl:
   - regression fix for might sleep in cursor handling

  nouveau:
   - regression fix in multi-screen cursor handling

  amdgpu:
   - switch off DC by default on Kaveri and older
   - some minor fixes

  i915:
   - some GEM regression fixes
   - doublescan mode fixes

  sun4i:
   - revert fix for a regression

  sii8620 bridge:
   - misc fixes"

* tag 'drm-fixes-2018-06-22' of git://anongit.freedesktop.org/drm/drm: (28 commits)
  drm/bridge/sii8620: fix display of packed pixel modes in MHL2
  drm/amdgpu: Make amdgpu_vram_mgr_bo_invisible_size always accurate
  drm/amdgpu: Refactor amdgpu_vram_mgr_bo_invisible_size helper
  drm/amdgpu: Update pin_size values before unpinning BO
  drm/amdgpu:All UVD instances share one idle_work handle
  drm/amdgpu: Don't default to DC support for Kaveri and older
  drm/amdgpu: Use kvmalloc_array for allocating VRAM manager nodes array
  drm/amd/pp: Fix uninitialized variable
  drm/i915: Enable provoking vertex fix on Gen9 systems.
  drm/i915: Fix context ban and hang accounting for client
  drm/i915: Turn off g4x DP port in .post_disable()
  drm/i915: Disallow interlaced modes on g4x DP outputs
  drm/i915: Fix PIPESTAT irq ack on i965/g4x
  drm/i915: Allow DBLSCAN user modes with eDP/LVDS/DSI
  drm/i915/execlists: Avoid putting the error pointer
  drm/i915: Apply batch location restrictions before pinning
  drm/nouveau/kms/nv50-: cursors always use core channel vram ctxdma
  Revert "drm/sun4i: Handle DRM_BUS_FLAG_PIXDATA_*EDGE"
  drm/atmel-hlcdc: check stride values in the first plane
  drm/bridge/sii8620: fix HDMI cable connection to dongle
  ...

1 files changed, 10 insertions, 14 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 5e4e1bd90383..3526efa8960e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -762,8 +762,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
         if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
                 adev->vram_pin_size += amdgpu_bo_size(bo);
-                if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
-                        adev->invisible_pin_size += amdgpu_bo_size(bo);
+                adev->invisible_pin_size += amdgpu_vram_mgr_bo_invisible_size(bo);
         } else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
                 adev->gart_pin_size += amdgpu_bo_size(bo);
         }
@@ -790,25 +789,22 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo)
         bo->pin_count--;
         if (bo->pin_count)
                 return 0;
-        for (i = 0; i < bo->placement.num_placement; i++) {
-                bo->placements[i].lpfn = 0;
-                bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
-        }
-        r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
-        if (unlikely(r)) {
-                dev_err(adev->dev, "%p validate failed for unpin\n", bo);
-                goto error;
-        }
 
         if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
                 adev->vram_pin_size -= amdgpu_bo_size(bo);
-                if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
-                        adev->invisible_pin_size -= amdgpu_bo_size(bo);
+                adev->invisible_pin_size -= amdgpu_vram_mgr_bo_invisible_size(bo);
         } else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
                 adev->gart_pin_size -= amdgpu_bo_size(bo);
         }
 
-error:
+        for (i = 0; i < bo->placement.num_placement; i++) {
+                bo->placements[i].lpfn = 0;
+                bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
+        }
+        r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
+        if (unlikely(r))
+                dev_err(adev->dev, "%p validate failed for unpin\n", bo);
+
         return r;
 }