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authorAlex Deucher <alexander.deucher@amd.com>2018-07-25 16:11:34 -0400
committerAlex Deucher <alexander.deucher@amd.com>2018-07-27 10:07:44 -0400
commitf1e582ebfd703ea01dc4caf4d339b7c84ec3ff29 (patch)
tree56bfd3cd4840cf6dee41cbbf77d468823065872b /drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
parentd04cc604a66b07eff8fce824fb6c0fdc0875d2e3 (diff)
drm/amdgpu: implement harvesting support for UVD 7.2 (v3)
Properly handle cases where one or more instance of the IP block may be harvested. v2: make sure ip_num_rings is initialized amdgpu_queue_mgr.c v3: rebase on Christian's UVD changes, drop unused var Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c17
1 files changed, 12 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index c7dce14fd47d..dd2132fa2b89 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -286,7 +286,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
286 struct drm_crtc *crtc; 286 struct drm_crtc *crtc;
287 uint32_t ui32 = 0; 287 uint32_t ui32 = 0;
288 uint64_t ui64 = 0; 288 uint64_t ui64 = 0;
289 int i, found; 289 int i, j, found;
290 int ui32_size = sizeof(ui32); 290 int ui32_size = sizeof(ui32);
291 291
292 if (!info->return_size || !info->return_pointer) 292 if (!info->return_size || !info->return_pointer)
@@ -348,7 +348,11 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
348 break; 348 break;
349 case AMDGPU_HW_IP_UVD: 349 case AMDGPU_HW_IP_UVD:
350 type = AMD_IP_BLOCK_TYPE_UVD; 350 type = AMD_IP_BLOCK_TYPE_UVD;
351 ring_mask |= adev->uvd.inst[0].ring.ready; 351 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
352 if (adev->uvd.harvest_config & (1 << i))
353 continue;
354 ring_mask |= adev->uvd.inst[i].ring.ready;
355 }
352 ib_start_alignment = 64; 356 ib_start_alignment = 64;
353 ib_size_alignment = 64; 357 ib_size_alignment = 64;
354 break; 358 break;
@@ -361,9 +365,12 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
361 break; 365 break;
362 case AMDGPU_HW_IP_UVD_ENC: 366 case AMDGPU_HW_IP_UVD_ENC:
363 type = AMD_IP_BLOCK_TYPE_UVD; 367 type = AMD_IP_BLOCK_TYPE_UVD;
364 for (i = 0; i < adev->uvd.num_enc_rings; i++) 368 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
365 ring_mask |= 369 if (adev->uvd.harvest_config & (1 << i))
366 adev->uvd.inst[0].ring_enc[i].ready << i; 370 continue;
371 for (j = 0; j < adev->uvd.num_enc_rings; j++)
372 ring_mask |= adev->uvd.inst[i].ring_enc[j].ready << j;
373 }
367 ib_start_alignment = 64; 374 ib_start_alignment = 64;
368 ib_size_alignment = 64; 375 ib_size_alignment = 64;
369 break; 376 break;