Merge branch 'drm-next-4.12' of git://people.freedesktop.org/~agd5f/linux into drm-next

New stuff for 4.12:
- Preliminary vega10 support
- Support for multi-level page tables
- GPU sensor stuff for mesa
- job tracing improvements
- PRT support for sparse buffers
- Additional SR-IOV improvements
- ttm improvements
- misc bug fixes and code cleanups

* 'drm-next-4.12' of git://people.freedesktop.org/~agd5f/linux: (315 commits)
  drm/amdgpu: Fix 32bit x86 compilation warning
  drm/amdgpu: just disallow reading untouched registers
  drm/amdgpu: remove duplicate allowed reg CP_CPF_BUSY_STAT
  drm/amdgpu/soc15: enable psp block for SRIOV
  drm/amdgpu/soc15: bypass pp block for vf
  drm/amdgpu/psp: add check sOS sign
  drm/amd/amdgpu: Correct ring wptr address in debugfs (v2)
  drm/amdgpu: Fix multi-level page table bugs for large BOs v3
  drm/amdgpu: Fix Vega10 VM initialization
  drm/amdgpu: Make max_pfn 64-bit
  drm/amdgpu: drop GB_GPU_ID from the golden settings
  drm/amdgpu: fix vm pte pde flags to 64-bit for sdma (v3)
  drm/amd/amdgpu: fix Tonga S3 resume hang on rhel6.8
  drm/ttm: decrease ttm bo priority number
  drm/amd/amdgpu: fix performance drop when VRAM pressure
  drm/amdgpu: Couple small warning fixes
  drm/amdgpu: Clean up GFX 9 VM fault messages
  drm/amdgpu: Register UTCL2 as a source of VM faults
  drm/amdgpu/soc15: drop support for reading some registers
  drm/amdgpu/soc15: return cached values for some registers (v2)
  ...

1 files changed, 131 insertions, 15 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 61d94c745672..5ded370a4b35 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -208,6 +208,14 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
                 break;
+        case AMDGPU_INFO_FW_SOS:
+                fw_info->ver = adev->psp.sos_fw_version;
+                fw_info->feature = adev->psp.sos_feature_version;
+                break;
+        case AMDGPU_INFO_FW_ASD:
+                fw_info->ver = adev->psp.asd_fw_version;
+                fw_info->feature = adev->psp.asd_feature_version;
+                break;
         default:
                 return -EINVAL;
         }
@@ -240,6 +248,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
         uint32_t ui32 = 0;
         uint64_t ui64 = 0;
         int i, found;
+        int ui32_size = sizeof(ui32);
 
         if (!info->return_size || !info->return_pointer)
                 return -EINVAL;
@@ -308,6 +317,13 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
                         ib_size_alignment = 1;
                         break;
+                case AMDGPU_HW_IP_UVD_ENC:
+                        type = AMD_IP_BLOCK_TYPE_UVD;
+                        for (i = 0; i < adev->uvd.num_enc_rings; i++)
+                                ring_mask |= ((adev->uvd.ring_enc[i].ready ? 1 : 0) << i);
+                        ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
+                        ib_size_alignment = 1;
+                        break;
                 default:
                         return -EINVAL;
                 }
@@ -347,6 +363,9 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                 case AMDGPU_HW_IP_VCE:
                         type = AMD_IP_BLOCK_TYPE_VCE;
                         break;
+                case AMDGPU_HW_IP_UVD_ENC:
+                        type = AMD_IP_BLOCK_TYPE_UVD;
+                        break;
                 default:
                         return -EINVAL;
                 }
@@ -527,6 +546,15 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                 dev_info.vram_type = adev->mc.vram_type;
                 dev_info.vram_bit_width = adev->mc.vram_width;
                 dev_info.vce_harvest_config = adev->vce.harvest_config;
+                dev_info.gc_double_offchip_lds_buf =
+                        adev->gfx.config.double_offchip_lds_buf;
+
+                if (amdgpu_ngg) {
+                        dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[PRIM].gpu_addr;
+                        dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[POS].gpu_addr;
+                        dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[CNTL].gpu_addr;
+                        dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[PARAM].gpu_addr;
+                }
 
                 return copy_to_user(out, &dev_info,
                                     min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
@@ -596,6 +624,80 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                         return -EINVAL;
                 }
         }
+        case AMDGPU_INFO_SENSOR: {
+                struct pp_gpu_power query = {0};
+                int query_size = sizeof(query);
+
+                if (amdgpu_dpm == 0)
+                        return -ENOENT;
+
+                switch (info->sensor_info.type) {
+                case AMDGPU_INFO_SENSOR_GFX_SCLK:
+                        /* get sclk in Mhz */
+                        if (amdgpu_dpm_read_sensor(adev,
+                                                   AMDGPU_PP_SENSOR_GFX_SCLK,
+                                                   (void *)&ui32, &ui32_size)) {
+                                return -EINVAL;
+                        }
+                        ui32 /= 100;
+                        break;
+                case AMDGPU_INFO_SENSOR_GFX_MCLK:
+                        /* get mclk in Mhz */
+                        if (amdgpu_dpm_read_sensor(adev,
+                                                   AMDGPU_PP_SENSOR_GFX_MCLK,
+                                                   (void *)&ui32, &ui32_size)) {
+                                return -EINVAL;
+                        }
+                        ui32 /= 100;
+                        break;
+                case AMDGPU_INFO_SENSOR_GPU_TEMP:
+                        /* get temperature in millidegrees C */
+                        if (amdgpu_dpm_read_sensor(adev,
+                                                   AMDGPU_PP_SENSOR_GPU_TEMP,
+                                                   (void *)&ui32, &ui32_size)) {
+                                return -EINVAL;
+                        }
+                        break;
+                case AMDGPU_INFO_SENSOR_GPU_LOAD:
+                        /* get GPU load */
+                        if (amdgpu_dpm_read_sensor(adev,
+                                                   AMDGPU_PP_SENSOR_GPU_LOAD,
+                                                   (void *)&ui32, &ui32_size)) {
+                                return -EINVAL;
+                        }
+                        break;
+                case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
+                        /* get average GPU power */
+                        if (amdgpu_dpm_read_sensor(adev,
+                                                   AMDGPU_PP_SENSOR_GPU_POWER,
+                                                   (void *)&query, &query_size)) {
+                                return -EINVAL;
+                        }
+                        ui32 = query.average_gpu_power >> 8;
+                        break;
+                case AMDGPU_INFO_SENSOR_VDDNB:
+                        /* get VDDNB in millivolts */
+                        if (amdgpu_dpm_read_sensor(adev,
+                                                   AMDGPU_PP_SENSOR_VDDNB,
+                                                   (void *)&ui32, &ui32_size)) {
+                                return -EINVAL;
+                        }
+                        break;
+                case AMDGPU_INFO_SENSOR_VDDGFX:
+                        /* get VDDGFX in millivolts */
+                        if (amdgpu_dpm_read_sensor(adev,
+                                                   AMDGPU_PP_SENSOR_VDDGFX,
+                                                   (void *)&ui32, &ui32_size)) {
+                                return -EINVAL;
+                        }
+                        break;
+                default:
+                        DRM_DEBUG_KMS("Invalid request %d\n",
+                                      info->sensor_info.type);
+                        return -EINVAL;
+                }
+                return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
+        }
         default:
                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
                 return -EINVAL;
@@ -655,6 +757,14 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
                 goto out_suspend;
         }
 
+        fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
+        if (!fpriv->prt_va) {
+                r = -ENOMEM;
+                amdgpu_vm_fini(adev, &fpriv->vm);
+                kfree(fpriv);
+                goto out_suspend;
+        }
+
         if (amdgpu_sriov_vf(adev)) {
                 r = amdgpu_map_static_csa(adev, &fpriv->vm);
                 if (r)
@@ -694,11 +804,15 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
         if (!fpriv)
                 return;
 
+        pm_runtime_get_sync(dev->dev);
+
         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
 
         amdgpu_uvd_free_handles(adev, file_priv);
         amdgpu_vce_free_handles(adev, file_priv);
 
+        amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
+
         if (amdgpu_sriov_vf(adev)) {
                 /* TODO: how to handle reserve failure */
                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, false));
@@ -722,21 +836,6 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
         pm_runtime_put_autosuspend(dev->dev);
 }
 
-/**
- * amdgpu_driver_preclose_kms - drm callback for pre close
- *
- * @dev: drm dev pointer
- * @file_priv: drm file
- *
- * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
- * (all asics).
- */
-void amdgpu_driver_preclose_kms(struct drm_device *dev,
-                                struct drm_file *file_priv)
-{
-        pm_runtime_get_sync(dev->dev);
-}
-
 /*
  * VBlank related functions.
  */
@@ -989,6 +1088,23 @@ static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
                            fw_info.feature, fw_info.ver);
         }
 
+        /* PSP SOS */
+        query_fw.fw_type = AMDGPU_INFO_FW_SOS;
+        ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
+        if (ret)
+                return ret;
+        seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
+                   fw_info.feature, fw_info.ver);
+
+
+        /* PSP ASD */
+        query_fw.fw_type = AMDGPU_INFO_FW_ASD;
+        ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
+        if (ret)
+                return ret;
+        seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
+                   fw_info.feature, fw_info.ver);
+
         /* SMC */
         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);