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authorJames Zhu <James.Zhu@amd.com>2018-05-15 15:25:46 -0400
committerAlex Deucher <alexander.deucher@amd.com>2018-05-18 17:08:12 -0400
commit2bb795f5ba9cd676536858a978b9df06f473af88 (patch)
tree1fbbc0d1e3e62668a925273db2139e31f4ed381c /drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
parent602ed6c69b128b77050e178aca9e945d969f3aa8 (diff)
drm/amdgpu/vg20:Restruct uvd to support multiple uvds
Vega20 has dual-UVD. Need Restruct amdgpu_device::uvd to support multiple uvds. There are no any logical changes here. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index eb4785e51573..5620ed291107 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -348,7 +348,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
348 break; 348 break;
349 case AMDGPU_HW_IP_UVD: 349 case AMDGPU_HW_IP_UVD:
350 type = AMD_IP_BLOCK_TYPE_UVD; 350 type = AMD_IP_BLOCK_TYPE_UVD;
351 ring_mask = adev->uvd.ring.ready ? 1 : 0; 351 ring_mask = adev->uvd.inst->ring.ready ? 1 : 0;
352 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 352 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
353 ib_size_alignment = 16; 353 ib_size_alignment = 16;
354 break; 354 break;
@@ -362,7 +362,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
362 case AMDGPU_HW_IP_UVD_ENC: 362 case AMDGPU_HW_IP_UVD_ENC:
363 type = AMD_IP_BLOCK_TYPE_UVD; 363 type = AMD_IP_BLOCK_TYPE_UVD;
364 for (i = 0; i < adev->uvd.num_enc_rings; i++) 364 for (i = 0; i < adev->uvd.num_enc_rings; i++)
365 ring_mask |= ((adev->uvd.ring_enc[i].ready ? 1 : 0) << i); 365 ring_mask |= ((adev->uvd.inst->ring_enc[i].ready ? 1 : 0) << i);
366 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 366 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
367 ib_size_alignment = 1; 367 ib_size_alignment = 1;
368 break; 368 break;