Merge branch 'drm-next-4.17' of git://people.freedesktop.org/~agd5f/linux into drm-next

- Continued cleanup and restructuring of powerplay
- Fetch VRAM type from vbios rather than hardcoding for SOC15 asics
- Allow ttm to drop its backing store when drivers don't need it
- DC bandwidth calc updates
- Enable DC backlight control pre-DCE11 asics
- Enable DC on all supported asics
- DC Fixes for planes due to the way our hw is ordered vs what drm expects
- DC CTM/regamma fixes
- Misc cleanup and bug fixes

* 'drm-next-4.17' of git://people.freedesktop.org/~agd5f/linux: (89 commits)
  amdgpu/dm: Default PRE_VEGA ASIC support to 'y'
  drm/amd/pp: Remove the cgs wrapper for notify smu version on APU
  drm/amd/display: fix dereferencing possible ERR_PTR()
  drm/amd/display: Refine disable VGA
  drm/amdgpu: Improve documentation of bo_ptr in amdgpu_bo_create_kernel
  drm/radeon: Don't turn off DP sink when disconnected
  drm/amd/pp: Rename file name cz_* to smu8_*
  drm/amd/pp: Replace function/struct name cz_* with smu8_*
  drm/amd/pp: Remove unneeded void * casts in cz_hwmgr.c/cz_smumgr.c
  drm/amd/pp: Mv cz uvd/vce pg/dpm functions to cz_hwmgr.c
  drm/amd/pp: Remove dead header file pp_asicblocks.h
  drm/amd/pp: Delete dead code on cz_clockpowergating.c
  drm/amdgpu: Call amdgpu_ucode_fini_bo in amd_powerplay.c
  drm/amdgpu: Remove wrapper layer of smu ip functions
  drm/amdgpu: Don't compared ip_block_type with ip_block_index
  drm/amdgpu: Plus NULL function pointer check
  drm/amd/pp: Move helper functions to smu_help.c
  drm/amd/pp: Replace rv_* with smu10_*
  drm/amd/pp: Fix function parameter not correct
  drm/amd/pp: Add rv_copy_table_from/to_smc to smu backend function table
  ...

1 files changed, 2 insertions, 41 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index b8a7dba69595..0e01f115bbe5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -25,51 +25,12 @@
 #define __AMDGPU_IH_H__
 
 #include <linux/chash.h>
+#include "soc15_ih_clientid.h"
 
 struct amdgpu_device;
- /*
-  * vega10+ IH clients
- */
-enum amdgpu_ih_clientid
-{
-    AMDGPU_IH_CLIENTID_IH           = 0x00,
-    AMDGPU_IH_CLIENTID_ACP          = 0x01,
-    AMDGPU_IH_CLIENTID_ATHUB        = 0x02,
-    AMDGPU_IH_CLIENTID_BIF          = 0x03,
-    AMDGPU_IH_CLIENTID_DCE          = 0x04,
-    AMDGPU_IH_CLIENTID_ISP          = 0x05,
-    AMDGPU_IH_CLIENTID_PCIE0        = 0x06,
-    AMDGPU_IH_CLIENTID_RLC          = 0x07,
-    AMDGPU_IH_CLIENTID_SDMA0        = 0x08,
-    AMDGPU_IH_CLIENTID_SDMA1        = 0x09,
-    AMDGPU_IH_CLIENTID_SE0SH        = 0x0a,
-    AMDGPU_IH_CLIENTID_SE1SH        = 0x0b,
-    AMDGPU_IH_CLIENTID_SE2SH        = 0x0c,
-    AMDGPU_IH_CLIENTID_SE3SH        = 0x0d,
-    AMDGPU_IH_CLIENTID_SYSHUB       = 0x0e,
-    AMDGPU_IH_CLIENTID_THM          = 0x0f,
-    AMDGPU_IH_CLIENTID_UVD          = 0x10,
-    AMDGPU_IH_CLIENTID_VCE0         = 0x11,
-    AMDGPU_IH_CLIENTID_VMC          = 0x12,
-    AMDGPU_IH_CLIENTID_XDMA         = 0x13,
-    AMDGPU_IH_CLIENTID_GRBM_CP      = 0x14,
-    AMDGPU_IH_CLIENTID_ATS          = 0x15,
-    AMDGPU_IH_CLIENTID_ROM_SMUIO    = 0x16,
-    AMDGPU_IH_CLIENTID_DF           = 0x17,
-    AMDGPU_IH_CLIENTID_VCE1         = 0x18,
-    AMDGPU_IH_CLIENTID_PWR          = 0x19,
-    AMDGPU_IH_CLIENTID_UTCL2        = 0x1b,
-    AMDGPU_IH_CLIENTID_EA           = 0x1c,
-    AMDGPU_IH_CLIENTID_UTCL2LOG     = 0x1d,
-    AMDGPU_IH_CLIENTID_MP0          = 0x1e,
-    AMDGPU_IH_CLIENTID_MP1          = 0x1f,
-
-    AMDGPU_IH_CLIENTID_MAX,
-
-    AMDGPU_IH_CLIENTID_VCN          = AMDGPU_IH_CLIENTID_UVD
-};
 
 #define AMDGPU_IH_CLIENTID_LEGACY 0
+#define AMDGPU_IH_CLIENTID_MAX SOC15_IH_CLIENTID_MAX
 
 #define AMDGPU_PAGEFAULT_HASH_BITS 8
 struct amdgpu_retryfault_hashtable {