drm/amdgpu: fix and cleanup user fence handling v2

We leaked the BO in the error pass, additional to that we only have
one user fence for all IBs in a job.

v2: remove white space changes

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 5 insertions, 4 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 201aceb01d8a..34e35423b78e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -203,10 +203,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
         }
 
         /* wrap the last IB with fence */
-        if (ib->user) {
-                uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo);
-                addr += ib->user->offset;
-                amdgpu_ring_emit_fence(ring, addr, ib->sequence,
+        if (job && job->uf_bo) {
+                uint64_t addr = amdgpu_bo_gpu_offset(job->uf_bo);
+
+                addr += job->uf_offset;
+                amdgpu_ring_emit_fence(ring, addr, job->uf_sequence,
                                        AMDGPU_FENCE_FLAG_64BIT);
         }