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authorMonk Liu <Monk.Liu@amd.com>2016-08-26 01:28:28 -0400
committerAlex Deucher <alexander.deucher@amd.com>2016-09-14 15:10:29 -0400
commit753ad49c9fdfc732972b0d03f2889f473ed35e59 (patch)
tree5b56188b3eb258fdcb167503979d657a0e9699be /drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
parent1db422de72c31fcf81f31311468a747aad389fa5 (diff)
drm/amdgpu:implement CONTEXT_CONTROL (v5)
v1: for gfx8, use CONTEXT_CONTROL package to dynamically skip preamble CEIB and other load_xxx command in sequence. v2: support GFX7 as well. remove cntxcntl in compute ring funcs because CPC doesn't support this packet. v3: fix reduntant judgement in cntxcntl. v4: some cleanups, don't change cs_submit() v5: keep old MESA supported & bump up KMS version. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Ack-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c12
1 files changed, 11 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 04263f0fd1af..2aa741c2a64c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -125,6 +125,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
125 unsigned patch_offset = ~0; 125 unsigned patch_offset = ~0;
126 struct amdgpu_vm *vm; 126 struct amdgpu_vm *vm;
127 uint64_t fence_ctx; 127 uint64_t fence_ctx;
128 uint32_t status = 0;
128 129
129 unsigned i; 130 unsigned i;
130 int r = 0; 131 int r = 0;
@@ -176,11 +177,20 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
176 177
177 skip_preamble = ring->current_ctx == fence_ctx; 178 skip_preamble = ring->current_ctx == fence_ctx;
178 need_ctx_switch = ring->current_ctx != fence_ctx; 179 need_ctx_switch = ring->current_ctx != fence_ctx;
180 if (job && ring->funcs->emit_cntxcntl) {
181 if (need_ctx_switch)
182 status |= AMDGPU_HAVE_CTX_SWITCH;
183 status |= job->preamble_status;
184 amdgpu_ring_emit_cntxcntl(ring, status);
185 }
186
179 for (i = 0; i < num_ibs; ++i) { 187 for (i = 0; i < num_ibs; ++i) {
180 ib = &ibs[i]; 188 ib = &ibs[i];
181 189
182 /* drop preamble IBs if we don't have a context switch */ 190 /* drop preamble IBs if we don't have a context switch */
183 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && skip_preamble) 191 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
192 skip_preamble &&
193 !(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST))
184 continue; 194 continue;
185 195
186 amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0, 196 amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0,