drm/amdgpu: add user fence context map v2

This is a prerequisite for the GPU scheduler to make the order
of submission independent from the order of execution.

v2: properly implement the locking

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>

1 files changed, 3 insertions, 1 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 2722815eddbb..95d533422a5b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -219,8 +219,10 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
         /* wrap the last IB with fence */
         if (ib->user) {
                 uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo);
+                ib->user->sequence = amdgpu_ctx_add_fence(ib->ctx, ring,
+                                                          &ib->fence->base);
                 addr += ib->user->offset;
-                amdgpu_ring_emit_fence(ring, addr, ib->fence->seq,
+                amdgpu_ring_emit_fence(ring, addr, ib->user->sequence,
                                        AMDGPU_FENCE_FLAG_64BIT);
         }