aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
diff options
context:
space:
mode:
authorHuang Rui <ray.huang@amd.com>2018-08-02 04:12:39 -0400
committerAlex Deucher <alexander.deucher@amd.com>2018-08-27 12:09:54 -0400
commit448fe1928ce415b8cae0425e5c7f066d6bd8b2de (patch)
treea187437c65eae3fcb8cd69640ede6254e454f8c2 /drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
parentfd28705388ef5244a963aa5ec70751d522c214c3 (diff)
drm/amdgpu: move gfx definitions into amdgpu_gfx header
Demangle amdgpu.h Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h349
1 files changed, 308 insertions, 41 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 1f279050d334..4e3d147c2f1b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -24,28 +24,296 @@
24#ifndef __AMDGPU_GFX_H__ 24#ifndef __AMDGPU_GFX_H__
25#define __AMDGPU_GFX_H__ 25#define __AMDGPU_GFX_H__
26 26
27int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg); 27/*
28void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg); 28 * GFX stuff
29 */
30#include "clearstate_defs.h"
31#include "amdgpu_ring.h"
29 32
30void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, 33/* GFX current status */
31 unsigned max_sh); 34#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
35#define AMDGPU_GFX_SAFE_MODE 0x00000001L
36#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
37#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
38#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
32 39
33void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
34 40
35int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, 41struct amdgpu_rlc_funcs {
36 struct amdgpu_ring *ring, 42 void (*enter_safe_mode)(struct amdgpu_device *adev);
37 struct amdgpu_irq_src *irq); 43 void (*exit_safe_mode)(struct amdgpu_device *adev);
44};
38 45
39void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring, 46struct amdgpu_rlc {
40 struct amdgpu_irq_src *irq); 47 /* for power gating */
48 struct amdgpu_bo *save_restore_obj;
49 uint64_t save_restore_gpu_addr;
50 volatile uint32_t *sr_ptr;
51 const u32 *reg_list;
52 u32 reg_list_size;
53 /* for clear state */
54 struct amdgpu_bo *clear_state_obj;
55 uint64_t clear_state_gpu_addr;
56 volatile uint32_t *cs_ptr;
57 const struct cs_section_def *cs_data;
58 u32 clear_state_size;
59 /* for cp tables */
60 struct amdgpu_bo *cp_table_obj;
61 uint64_t cp_table_gpu_addr;
62 volatile uint32_t *cp_table_ptr;
63 u32 cp_table_size;
41 64
42void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev); 65 /* safe mode for updating CG/PG state */
43int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, 66 bool in_safe_mode;
44 unsigned hpd_size); 67 const struct amdgpu_rlc_funcs *funcs;
45 68
46int amdgpu_gfx_compute_mqd_sw_init(struct amdgpu_device *adev, 69 /* for firmware data */
47 unsigned mqd_size); 70 u32 save_and_restore_offset;
48void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device *adev); 71 u32 clear_state_descriptor_offset;
72 u32 avail_scratch_ram_locations;
73 u32 reg_restore_list_size;
74 u32 reg_list_format_start;
75 u32 reg_list_format_separate_start;
76 u32 starting_offsets_start;
77 u32 reg_list_format_size_bytes;
78 u32 reg_list_size_bytes;
79 u32 reg_list_format_direct_reg_list_length;
80 u32 save_restore_list_cntl_size_bytes;
81 u32 save_restore_list_gpm_size_bytes;
82 u32 save_restore_list_srm_size_bytes;
83
84 u32 *register_list_format;
85 u32 *register_restore;
86 u8 *save_restore_list_cntl;
87 u8 *save_restore_list_gpm;
88 u8 *save_restore_list_srm;
89
90 bool is_rlc_v2_1;
91};
92
93#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
94
95struct amdgpu_mec {
96 struct amdgpu_bo *hpd_eop_obj;
97 u64 hpd_eop_gpu_addr;
98 struct amdgpu_bo *mec_fw_obj;
99 u64 mec_fw_gpu_addr;
100 u32 num_mec;
101 u32 num_pipe_per_mec;
102 u32 num_queue_per_pipe;
103 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
104
105 /* These are the resources for which amdgpu takes ownership */
106 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
107};
108
109struct amdgpu_kiq {
110 u64 eop_gpu_addr;
111 struct amdgpu_bo *eop_obj;
112 spinlock_t ring_lock;
113 struct amdgpu_ring ring;
114 struct amdgpu_irq_src irq;
115};
116
117/*
118 * GPU scratch registers structures, functions & helpers
119 */
120struct amdgpu_scratch {
121 unsigned num_reg;
122 uint32_t reg_base;
123 uint32_t free_mask;
124};
125
126/*
127 * GFX configurations
128 */
129#define AMDGPU_GFX_MAX_SE 4
130#define AMDGPU_GFX_MAX_SH_PER_SE 2
131
132struct amdgpu_rb_config {
133 uint32_t rb_backend_disable;
134 uint32_t user_rb_backend_disable;
135 uint32_t raster_config;
136 uint32_t raster_config_1;
137};
138
139struct gb_addr_config {
140 uint16_t pipe_interleave_size;
141 uint8_t num_pipes;
142 uint8_t max_compress_frags;
143 uint8_t num_banks;
144 uint8_t num_se;
145 uint8_t num_rb_per_se;
146};
147
148struct amdgpu_gfx_config {
149 unsigned max_shader_engines;
150 unsigned max_tile_pipes;
151 unsigned max_cu_per_sh;
152 unsigned max_sh_per_se;
153 unsigned max_backends_per_se;
154 unsigned max_texture_channel_caches;
155 unsigned max_gprs;
156 unsigned max_gs_threads;
157 unsigned max_hw_contexts;
158 unsigned sc_prim_fifo_size_frontend;
159 unsigned sc_prim_fifo_size_backend;
160 unsigned sc_hiz_tile_fifo_size;
161 unsigned sc_earlyz_tile_fifo_size;
162
163 unsigned num_tile_pipes;
164 unsigned backend_enable_mask;
165 unsigned mem_max_burst_length_bytes;
166 unsigned mem_row_size_in_kb;
167 unsigned shader_engine_tile_size;
168 unsigned num_gpus;
169 unsigned multi_gpu_tile_size;
170 unsigned mc_arb_ramcfg;
171 unsigned gb_addr_config;
172 unsigned num_rbs;
173 unsigned gs_vgt_table_depth;
174 unsigned gs_prim_buffer_depth;
175
176 uint32_t tile_mode_array[32];
177 uint32_t macrotile_mode_array[16];
178
179 struct gb_addr_config gb_addr_config_fields;
180 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
181
182 /* gfx configure feature */
183 uint32_t double_offchip_lds_buf;
184 /* cached value of DB_DEBUG2 */
185 uint32_t db_debug2;
186};
187
188struct amdgpu_cu_info {
189 uint32_t simd_per_cu;
190 uint32_t max_waves_per_simd;
191 uint32_t wave_front_size;
192 uint32_t max_scratch_slots_per_cu;
193 uint32_t lds_size;
194
195 /* total active CU number */
196 uint32_t number;
197 uint32_t ao_cu_mask;
198 uint32_t ao_cu_bitmap[4][4];
199 uint32_t bitmap[4][4];
200};
201
202struct amdgpu_gfx_funcs {
203 /* get the gpu clock counter */
204 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
205 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
206 u32 sh_num, u32 instance);
207 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
208 uint32_t wave, uint32_t *dst, int *no_fields);
209 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
210 uint32_t wave, uint32_t thread, uint32_t start,
211 uint32_t size, uint32_t *dst);
212 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
213 uint32_t wave, uint32_t start, uint32_t size,
214 uint32_t *dst);
215 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
216 u32 queue);
217};
218
219struct amdgpu_ngg_buf {
220 struct amdgpu_bo *bo;
221 uint64_t gpu_addr;
222 uint32_t size;
223 uint32_t bo_size;
224};
225
226enum {
227 NGG_PRIM = 0,
228 NGG_POS,
229 NGG_CNTL,
230 NGG_PARAM,
231 NGG_BUF_MAX
232};
233
234struct amdgpu_ngg {
235 struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
236 uint32_t gds_reserve_addr;
237 uint32_t gds_reserve_size;
238 bool init;
239};
240
241struct sq_work {
242 struct work_struct work;
243 unsigned ih_data;
244};
245
246struct amdgpu_gfx {
247 struct mutex gpu_clock_mutex;
248 struct amdgpu_gfx_config config;
249 struct amdgpu_rlc rlc;
250 struct amdgpu_mec mec;
251 struct amdgpu_kiq kiq;
252 struct amdgpu_scratch scratch;
253 const struct firmware *me_fw; /* ME firmware */
254 uint32_t me_fw_version;
255 const struct firmware *pfp_fw; /* PFP firmware */
256 uint32_t pfp_fw_version;
257 const struct firmware *ce_fw; /* CE firmware */
258 uint32_t ce_fw_version;
259 const struct firmware *rlc_fw; /* RLC firmware */
260 uint32_t rlc_fw_version;
261 const struct firmware *mec_fw; /* MEC firmware */
262 uint32_t mec_fw_version;
263 const struct firmware *mec2_fw; /* MEC2 firmware */
264 uint32_t mec2_fw_version;
265 uint32_t me_feature_version;
266 uint32_t ce_feature_version;
267 uint32_t pfp_feature_version;
268 uint32_t rlc_feature_version;
269 uint32_t rlc_srlc_fw_version;
270 uint32_t rlc_srlc_feature_version;
271 uint32_t rlc_srlg_fw_version;
272 uint32_t rlc_srlg_feature_version;
273 uint32_t rlc_srls_fw_version;
274 uint32_t rlc_srls_feature_version;
275 uint32_t mec_feature_version;
276 uint32_t mec2_feature_version;
277 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
278 unsigned num_gfx_rings;
279 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
280 unsigned num_compute_rings;
281 struct amdgpu_irq_src eop_irq;
282 struct amdgpu_irq_src priv_reg_irq;
283 struct amdgpu_irq_src priv_inst_irq;
284 struct amdgpu_irq_src cp_ecc_error_irq;
285 struct amdgpu_irq_src sq_irq;
286 struct sq_work sq_work;
287
288 /* gfx status */
289 uint32_t gfx_current_status;
290 /* ce ram size*/
291 unsigned ce_ram_size;
292 struct amdgpu_cu_info cu_info;
293 const struct amdgpu_gfx_funcs *funcs;
294
295 /* reset mask */
296 uint32_t grbm_soft_reset;
297 uint32_t srbm_soft_reset;
298 /* s3/s4 mask */
299 bool in_suspend;
300 /* NGG */
301 struct amdgpu_ngg ngg;
302
303 /* gfx off */
304 bool gfx_off_state; /* true: enabled, false: disabled */
305 struct mutex gfx_off_mutex;
306 uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */
307 struct delayed_work gfx_off_delay_work;
308
309 /* pipe reservation */
310 struct mutex pipe_reserve_mutex;
311 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
312};
313
314#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
315#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
316#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q))
49 317
50/** 318/**
51 * amdgpu_gfx_create_bitmask - create a bitmask 319 * amdgpu_gfx_create_bitmask - create a bitmask
@@ -60,34 +328,33 @@ static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
60 return (u32)((1ULL << bit_width) - 1); 328 return (u32)((1ULL << bit_width) - 1);
61} 329}
62 330
63static inline int amdgpu_gfx_queue_to_bit(struct amdgpu_device *adev, 331int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg);
64 int mec, int pipe, int queue) 332void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);
65{
66 int bit = 0;
67 333
68 bit += mec * adev->gfx.mec.num_pipe_per_mec 334void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
69 * adev->gfx.mec.num_queue_per_pipe; 335 unsigned max_sh);
70 bit += pipe * adev->gfx.mec.num_queue_per_pipe;
71 bit += queue;
72 336
73 return bit; 337int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
74} 338 struct amdgpu_ring *ring,
339 struct amdgpu_irq_src *irq);
75 340
76static inline void amdgpu_gfx_bit_to_queue(struct amdgpu_device *adev, int bit, 341void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring,
77 int *mec, int *pipe, int *queue) 342 struct amdgpu_irq_src *irq);
78{
79 *queue = bit % adev->gfx.mec.num_queue_per_pipe;
80 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
81 % adev->gfx.mec.num_pipe_per_mec;
82 *mec = (bit / adev->gfx.mec.num_queue_per_pipe)
83 / adev->gfx.mec.num_pipe_per_mec;
84 343
85} 344void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
86static inline bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, 345int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
87 int mec, int pipe, int queue) 346 unsigned hpd_size);
88{ 347
89 return test_bit(amdgpu_gfx_queue_to_bit(adev, mec, pipe, queue), 348int amdgpu_gfx_compute_mqd_sw_init(struct amdgpu_device *adev,
90 adev->gfx.mec.queue_bitmap); 349 unsigned mqd_size);
91} 350void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device *adev);
351
352void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
353int amdgpu_gfx_queue_to_bit(struct amdgpu_device *adev, int mec,
354 int pipe, int queue);
355void amdgpu_gfx_bit_to_queue(struct amdgpu_device *adev, int bit,
356 int *mec, int *pipe, int *queue);
357bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
358 int pipe, int queue);
92 359
93#endif 360#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-27 09:49:37 -0400