drm/amdgpu: acquire available gfx queues

currently, amdgpu will owns the first gfx queue of each pipe
they are:
me:0 pipe:0 queue:0
me:0 pipe:1 queue:0

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 24 insertions, 0 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 997932ebbb83..855eff834e2a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -199,6 +199,30 @@ void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
                 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
 }
 
+void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)
+{
+        int i, queue, pipe, me;
+
+        for (i = 0; i < AMDGPU_MAX_GFX_QUEUES; ++i) {
+                queue = i % adev->gfx.me.num_queue_per_pipe;
+                pipe = (i / adev->gfx.me.num_queue_per_pipe)
+                        % adev->gfx.me.num_pipe_per_me;
+                me = (i / adev->gfx.me.num_queue_per_pipe)
+                      / adev->gfx.me.num_pipe_per_me;
+
+                if (me >= adev->gfx.me.num_me)
+                        break;
+                /* policy: amdgpu owns the first queue per pipe at this stage
+                 * will extend to mulitple queues per pipe later */
+                if (me == 0 && queue < 1)
+                        set_bit(i, adev->gfx.me.queue_bitmap);
+        }
+
+        /* update the number of active graphics rings */
+        adev->gfx.num_gfx_rings =
+                bitmap_weight(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
+}
+
 static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,
                                   struct amdgpu_ring *ring)
 {