drm/amdgpu: move gfx definitions into amdgpu_gfx header

Demangle amdgpu.h

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 33 insertions, 1 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 11d4d9f93b95..bbb81e23020e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -30,8 +30,40 @@
 #define GFX_OFF_DELAY_ENABLE         msecs_to_jiffies(500)
 
 /*
- * GPU scratch registers helpers function.
+ * GPU GFX IP block helpers function.
  */
+
+int amdgpu_gfx_queue_to_bit(struct amdgpu_device *adev, int mec,
+                            int pipe, int queue)
+{
+        int bit = 0;
+
+        bit += mec * adev->gfx.mec.num_pipe_per_mec
+                * adev->gfx.mec.num_queue_per_pipe;
+        bit += pipe * adev->gfx.mec.num_queue_per_pipe;
+        bit += queue;
+
+        return bit;
+}
+
+void amdgpu_gfx_bit_to_queue(struct amdgpu_device *adev, int bit,
+                             int *mec, int *pipe, int *queue)
+{
+        *queue = bit % adev->gfx.mec.num_queue_per_pipe;
+        *pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
+                % adev->gfx.mec.num_pipe_per_mec;
+        *mec = (bit / adev->gfx.mec.num_queue_per_pipe)
+               / adev->gfx.mec.num_pipe_per_mec;
+
+}
+
+bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,
+                                     int mec, int pipe, int queue)
+{
+        return test_bit(amdgpu_gfx_queue_to_bit(adev, mec, pipe, queue),
+                        adev->gfx.mec.queue_bitmap);
+}
+
 /**
  * amdgpu_gfx_scratch_get - Allocate a scratch register
  *