Merge branch 'drm-next-4.14' of git://people.freedesktop.org/~agd5f/linux into drm-next

- Stop reprogramming the MC, the vbios already does this in asic_init
- Reduce internal gart to 256M (this does not affect the ttm GTT pool size)
- Initial support for huge pages
- Rework bo migration logic
- Lots of improvements for vega10
- Powerplay fixes
- Additional Raven enablement
- SR-IOV improvements
- Bug fixes
- Code cleanup

* 'drm-next-4.14' of git://people.freedesktop.org/~agd5f/linux: (138 commits)
  drm/amdgpu: fix header on gfx9 clear state
  drm/amdgpu: reduce the time of reading VBIOS
  drm/amdgpu/virtual_dce: Remove the rmmod error message
  drm/amdgpu/gmc9: disable legacy vga features in gmc init
  drm/amdgpu/gmc8: disable legacy vga features in gmc init
  drm/amdgpu/gmc7: disable legacy vga features in gmc init
  drm/amdgpu/gmc6: disable legacy vga features in gmc init (v2)
  drm/radeon: Set depth on low mem to 16 bpp instead of 8 bpp
  drm/amdgpu: fix the incorrect scratch reg number on gfx v6
  drm/amdgpu: fix the incorrect scratch reg number on gfx v7
  drm/amdgpu: fix the incorrect scratch reg number on gfx v8
  drm/amdgpu: fix the incorrect scratch reg number on gfx v9
  drm/amd/powerplay: add support for 3DP 4K@120Hz on vega10.
  drm/amdgpu: enable huge page handling in the VM v5
  drm/amdgpu: increase fragmentation size for Vega10 v2
  drm/amdgpu: ttm_bind only when user needs gpu_addr in bo pin
  drm/amdgpu: correct clock info for SRIOV
  drm/amdgpu/gmc8: SRIOV need to program fb location
  drm/amdgpu: disable firmware loading for psp v10
  drm/amdgpu:fix gfx fence allocate size
  ...

1 files changed, 7 insertions, 15 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 621f739103a6..917ac5e074a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -49,7 +49,6 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
                                 struct drm_gem_object **obj)
 {
         struct amdgpu_bo *robj;
-        unsigned long max_size;
         int r;
 
         *obj = NULL;
@@ -58,17 +57,6 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
                 alignment = PAGE_SIZE;
         }
 
-        if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) {
-                /* Maximum bo size is the unpinned gtt size since we use the gtt to
-                 * handle vram to system pool migrations.
-                 */
-                max_size = adev->mc.gtt_size - adev->gart_pin_size;
-                if (size > max_size) {
-                        DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n",
-                                  size >> 20, max_size >> 20);
-                        return -ENOMEM;
-                }
-        }
 retry:
         r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
                              flags, NULL, NULL, &robj);
@@ -784,6 +772,7 @@ static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
         unsigned domain;
         const char *placement;
         unsigned pin_count;
+        uint64_t offset;
 
         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
         switch (domain) {
@@ -798,9 +787,12 @@ static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
                 placement = " CPU";
                 break;
         }
-        seq_printf(m, "\t0x%08x: %12ld byte %s @ 0x%010Lx",
-                   id, amdgpu_bo_size(bo), placement,
-                   amdgpu_bo_gpu_offset(bo));
+        seq_printf(m, "\t0x%08x: %12ld byte %s",
+                   id, amdgpu_bo_size(bo), placement);
+
+        offset = ACCESS_ONCE(bo->tbo.mem.start);
+        if (offset != AMDGPU_BO_INVALID_OFFSET)
+                seq_printf(m, " @ 0x%010Lx", offset);
 
         pin_count = ACCESS_ONCE(bo->pin_count);
         if (pin_count)