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authorpding <Pixel.Ding@amd.com>2017-10-12 01:53:20 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-10-19 15:27:18 -0400
commite71de0766191d32648cf12dfb2f53f05e52b2dcc (patch)
tree1d80f99f733d73191d6052798a62e0999d92bcc4 /drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
parentf993d628a2d3cb5e0a82a5284b24cef745f42b41 (diff)
drm/amdgpu: report more amdgpu_fence_info
Only for GFX ring. This can help checking MCBP feature. The fence at the end of the frame will indicate the completion status. If the frame completed normally, the fence is written to the address given in the EVENT_WRITE_EOP packet. If preemption occurred in the previous IB the address is adjusted by 2 DWs. If work submitted in the frame was reset before completion, the fence address is adjusted by four DWs. In the case that preemption occurred, and before preemption completed a reset was initiated, the address will be adjusted with six DWs Signed-off-by: pding <Pixel.Ding@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 333bad749067..7bdedd788f5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -641,6 +641,19 @@ static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
641 atomic_read(&ring->fence_drv.last_seq)); 641 atomic_read(&ring->fence_drv.last_seq));
642 seq_printf(m, "Last emitted 0x%08x\n", 642 seq_printf(m, "Last emitted 0x%08x\n",
643 ring->fence_drv.sync_seq); 643 ring->fence_drv.sync_seq);
644
645 if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
646 continue;
647
648 /* set in CP_VMID_PREEMPT and preemption occurred */
649 seq_printf(m, "Last preempted 0x%08x\n",
650 le32_to_cpu(*(ring->fence_drv.cpu_addr + 2)));
651 /* set in CP_VMID_RESET and reset occurred */
652 seq_printf(m, "Last reset 0x%08x\n",
653 le32_to_cpu(*(ring->fence_drv.cpu_addr + 4)));
654 /* Both preemption and reset occurred */
655 seq_printf(m, "Last both 0x%08x\n",
656 le32_to_cpu(*(ring->fence_drv.cpu_addr + 6)));
644 } 657 }
645 return 0; 658 return 0;
646} 659}