diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2016-01-14 10:25:22 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2016-02-10 14:16:55 -0500 |
commit | 18db89b4025a9fb71824d0ffd84594c9f6f41cec (patch) | |
tree | 023aa1127b29768083750a0c06821f00544b6079 /drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | |
parent | bfa99269ea6c6ca9e75bdddb92f0afce875fb010 (diff) |
drm/amdgpu: add a debugfs property to trigger a GPU reset
Ported from similar code in radeon.
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 988a32d578a0..08963fc83168 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | |||
@@ -734,15 +734,33 @@ static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data) | |||
734 | return 0; | 734 | return 0; |
735 | } | 735 | } |
736 | 736 | ||
737 | /** | ||
738 | * amdgpu_debugfs_gpu_reset - manually trigger a gpu reset | ||
739 | * | ||
740 | * Manually trigger a gpu reset at the next fence wait. | ||
741 | */ | ||
742 | static int amdgpu_debugfs_gpu_reset(struct seq_file *m, void *data) | ||
743 | { | ||
744 | struct drm_info_node *node = (struct drm_info_node *) m->private; | ||
745 | struct drm_device *dev = node->minor->dev; | ||
746 | struct amdgpu_device *adev = dev->dev_private; | ||
747 | |||
748 | seq_printf(m, "gpu reset\n"); | ||
749 | amdgpu_gpu_reset(adev); | ||
750 | |||
751 | return 0; | ||
752 | } | ||
753 | |||
737 | static struct drm_info_list amdgpu_debugfs_fence_list[] = { | 754 | static struct drm_info_list amdgpu_debugfs_fence_list[] = { |
738 | {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, | 755 | {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, |
756 | {"amdgpu_gpu_reset", &amdgpu_debugfs_gpu_reset, 0, NULL} | ||
739 | }; | 757 | }; |
740 | #endif | 758 | #endif |
741 | 759 | ||
742 | int amdgpu_debugfs_fence_init(struct amdgpu_device *adev) | 760 | int amdgpu_debugfs_fence_init(struct amdgpu_device *adev) |
743 | { | 761 | { |
744 | #if defined(CONFIG_DEBUG_FS) | 762 | #if defined(CONFIG_DEBUG_FS) |
745 | return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 1); | 763 | return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 2); |
746 | #else | 764 | #else |
747 | return 0; | 765 | return 0; |
748 | #endif | 766 | #endif |