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authorRex Zhu <Rex.Zhu@amd.com>2018-06-05 01:06:11 -0400
committerAlex Deucher <alexander.deucher@amd.com>2018-07-05 17:38:48 -0400
commitb92c628712ed3a1cf5d4a144290e8ffc170bf51e (patch)
tree049bc880c00dd06136bcb3eb1e4555c998bf14b0 /drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
parent3eb6e4795de3171d5c59f9368f48bb770087de77 (diff)
drm/amd/pp: Unify powergate_uvd/vce/mmhub to set_powergating_by_smu
Some HW ip blocks need call SMU to enter/leave power gate state. So export common set_powergating_by_smu interface. 1. keep consistent with set_clockgating_by_smu 2. scales easily to powergate other ip(gfx) if necessary Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h14
1 files changed, 4 insertions, 10 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index c6d692625687..ff24e1cc5b65 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -287,12 +287,6 @@ enum amdgpu_pcie_gen {
287#define amdgpu_dpm_force_performance_level(adev, l) \ 287#define amdgpu_dpm_force_performance_level(adev, l) \
288 ((adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l))) 288 ((adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)))
289 289
290#define amdgpu_dpm_powergate_uvd(adev, g) \
291 ((adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)))
292
293#define amdgpu_dpm_powergate_vce(adev, g) \
294 ((adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)))
295
296#define amdgpu_dpm_get_current_power_state(adev) \ 290#define amdgpu_dpm_get_current_power_state(adev) \
297 ((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)) 291 ((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))
298 292
@@ -347,6 +341,10 @@ enum amdgpu_pcie_gen {
347 ((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\ 341 ((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\
348 (adev)->powerplay.pp_handle, msg_id)) 342 (adev)->powerplay.pp_handle, msg_id))
349 343
344#define amdgpu_dpm_set_powergating_by_smu(adev, block_type, gate) \
345 ((adev)->powerplay.pp_funcs->set_powergating_by_smu(\
346 (adev)->powerplay.pp_handle, block_type, gate))
347
350#define amdgpu_dpm_get_power_profile_mode(adev, buf) \ 348#define amdgpu_dpm_get_power_profile_mode(adev, buf) \
351 ((adev)->powerplay.pp_funcs->get_power_profile_mode(\ 349 ((adev)->powerplay.pp_funcs->get_power_profile_mode(\
352 (adev)->powerplay.pp_handle, buf)) 350 (adev)->powerplay.pp_handle, buf))
@@ -359,10 +357,6 @@ enum amdgpu_pcie_gen {
359 ((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\ 357 ((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
360 (adev)->powerplay.pp_handle, type, parameter, size)) 358 (adev)->powerplay.pp_handle, type, parameter, size))
361 359
362#define amdgpu_dpm_powergate_mmhub(adev) \
363 ((adev)->powerplay.pp_funcs->powergate_mmhub( \
364 (adev)->powerplay.pp_handle))
365
366struct amdgpu_dpm { 360struct amdgpu_dpm {
367 struct amdgpu_ps *ps; 361 struct amdgpu_ps *ps;
368 /* number of valid power states */ 362 /* number of valid power states */