drm/amd/amdgpu: add power profile sysfs entry

Add the sysfs entries pp_gfx_power_profile and
pp_compute_power_profile which give user a way to set
power profile through parameters minimum sclk, minimum mclk,
activity threshold, up hysteresis and down hysteresis only
when the entry power_dpm_force_performance_level is in
default value "auto". It is read and write. Example:

echo 500 800 20 0 5 > /sys/class/drm/card0/device/pp_*_power_profile

cat /sys/class/drm/card0/device/pp_*_power_profile
500 800 20 0 5

Note: first parameter is sclk in MHz, second is mclk in MHz,
third is activity threshold in percentage, fourth is up hysteresis
in ms and fifth is down hysteresis in ms.

echo set > /sys/class/drm/card0/device/pp_*_power_profile
To set power profile state if it exists.

echo reset > /sys/class/drm/card0/device/pp_*_power_profile
To restore default state and clear previous setting.

Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Acked-by: Rex Zhu <Rex.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 24 insertions, 0 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index fa2b55681422..5f09893c9674 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -272,6 +272,14 @@ struct amdgpu_dpm_funcs {
                                 bool *equal);
 
         struct amd_vce_state* (*get_vce_clock_state)(struct amdgpu_device *adev, unsigned idx);
+        int (*reset_power_profile_state)(struct amdgpu_device *adev,
+                        struct amd_pp_profile *request);
+        int (*get_power_profile_state)(struct amdgpu_device *adev,
+                        struct amd_pp_profile *query);
+        int (*set_power_profile_state)(struct amdgpu_device *adev,
+                        struct amd_pp_profile *request);
+        int (*switch_power_profile)(struct amdgpu_device *adev,
+                        enum amd_pp_profile_type type);
 };
 
 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
@@ -388,6 +396,22 @@ struct amdgpu_dpm_funcs {
         (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle) : \
         (adev)->pm.dpm.forced_level)
 
+#define amdgpu_dpm_reset_power_profile_state(adev, request) \
+        ((adev)->powerplay.pp_funcs->reset_power_profile_state(\
+                        (adev)->powerplay.pp_handle, request))
+
+#define amdgpu_dpm_get_power_profile_state(adev, query) \
+        ((adev)->powerplay.pp_funcs->get_power_profile_state(\
+                        (adev)->powerplay.pp_handle, query))
+
+#define amdgpu_dpm_set_power_profile_state(adev, request) \
+        ((adev)->powerplay.pp_funcs->set_power_profile_state(\
+                        (adev)->powerplay.pp_handle, request))
+
+#define amdgpu_dpm_switch_power_profile(adev, type) \
+        ((adev)->powerplay.pp_funcs->switch_power_profile(\
+                        (adev)->powerplay.pp_handle, type))
+
 struct amdgpu_dpm {
         struct amdgpu_ps        *ps;
         /* number of valid power states */