drm/amdgpu: Load fw between hw_init/resume_phase1 and phase2

Extract the function of fw loading out of powerplay.
Do fw loading between hw_init/resuem_phase1 and phase2

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 60 insertions, 1 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 372574abc1c4..1e4dd09a5072 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1570,6 +1570,47 @@ static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
         return 0;
 }
 
+static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
+{
+        int r = 0;
+        int i;
+
+        if (adev->asic_type >= CHIP_VEGA10) {
+                for (i = 0; i < adev->num_ip_blocks; i++) {
+                        if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
+                                if (adev->in_gpu_reset || adev->in_suspend) {
+                                        if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset)
+                                                break; /* sriov gpu reset, psp need to do hw_init before IH because of hw limit */
+                                        r = adev->ip_blocks[i].version->funcs->resume(adev);
+                                        if (r) {
+                                                DRM_ERROR("resume of IP block <%s> failed %d\n",
+                                                          adev->ip_blocks[i].version->funcs->name, r);
+                                                return r;
+                                        }
+                                } else {
+                                        r = adev->ip_blocks[i].version->funcs->hw_init(adev);
+                                        if (r) {
+                                                DRM_ERROR("hw_init of IP block <%s> failed %d\n",
+                                                  adev->ip_blocks[i].version->funcs->name, r);
+                                                return r;
+                                        }
+                                }
+                                adev->ip_blocks[i].status.hw = true;
+                        }
+                }
+        }
+
+        if (adev->powerplay.pp_funcs->load_firmware) {
+                r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
+                if (r) {
+                        pr_err("firmware loading failed\n");
+                        return r;
+                }
+        }
+
+        return 0;
+}
+
 /**
  * amdgpu_device_ip_init - run init for hardware IPs
  *
@@ -1634,6 +1675,10 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
         if (r)
                 return r;
 
+        r = amdgpu_device_fw_loading(adev);
+        if (r)
+                return r;
+
         r = amdgpu_device_ip_hw_init_phase2(adev);
         if (r)
                 return r;
@@ -2167,7 +2212,8 @@ static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
                         continue;
                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
-                    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)
+                    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
+                    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
                         continue;
                 r = adev->ip_blocks[i].version->funcs->resume(adev);
                 if (r) {
@@ -2199,6 +2245,11 @@ static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
         r = amdgpu_device_ip_resume_phase1(adev);
         if (r)
                 return r;
+
+        r = amdgpu_device_fw_loading(adev);
+        if (r)
+                return r;
+
         r = amdgpu_device_ip_resume_phase2(adev);
 
         return r;
@@ -3149,6 +3200,10 @@ retry:
                         if (r)
                                 goto out;
 
+                        r = amdgpu_device_fw_loading(adev);
+                        if (r)
+                                return r;
+
                         r = amdgpu_device_ip_resume_phase2(adev);
                         if (r)
                                 goto out;
@@ -3205,6 +3260,10 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
         /* we need recover gart prior to run SMC/CP/SDMA resume */
         amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]);
 
+        r = amdgpu_device_fw_loading(adev);
+        if (r)
+                return r;
+
         /* now we are okay to resume SMC/CP/SDMA */
         r = amdgpu_device_ip_reinit_late_sriov(adev);
         if (r)