Merge tag 'drm-next-2018-10-24' of git://anongit.freedesktop.org/drm/drm

Pull drm updates from Dave Airlie:
 "This is going to rebuild more than drm as it adds a new helper to
  list.h for doing bulk updates. Seemed like a reasonable addition to
  me.

  Otherwise the usual merge window stuff lots of i915 and amdgpu, not so
  much nouveau, and piles of everything else.

  Core:
   - Adds a new list.h helper for doing bulk list updates for TTM.
   - Don't leak fb address in smem_start to userspace (comes with EXPORT
     workaround for people using mali out of tree hacks)
   - udmabuf device to turn memfd regions into dma-buf
   - Per-plane blend mode property
   - ref/unref replacements with get/put
   - fbdev conflicting framebuffers code cleaned up
   - host-endian format variants
   - panel orientation quirk for Acer One 10

  bridge:
   - TI SN65DSI86 chip support

  vkms:
   - GEM support.
   - Cursor support

  amdgpu:
   - Merge amdkfd and amdgpu into one module
   - CEC over DP AUX support
   - Picasso APU support + VCN dynamic powergating
   - Raven2 APU support
   - Vega20 enablement + kfd support
   - ACP powergating improvements
   - ABGR/XBGR display support
   - VCN jpeg support
   - xGMI support
   - DC i2c/aux cleanup
   - Ycbcr 4:2:0 support
   - GPUVM improvements
   - Powerplay and powerplay endian fixes
   - Display underflow fixes

  vmwgfx:
   - Move vmwgfx specific TTM code to vmwgfx
   - Split out vmwgfx buffer/resource validation code
   - Atomic operation rework

  bochs:
   - use more helpers
   - format/byteorder improvements

  qxl:
   - use more helpers

  i915:
   - GGTT coherency getparam
   - Turn off resource streamer API
   - More Icelake enablement + DMC firmware
   - Full PPGTT for Ivybridge, Haswell and Valleyview
   - DDB distribution based on resolution
   - Limited range DP display support

  nouveau:
   - CEC over DP AUX support
   - Initial HDMI 2.0 support

  virtio-gpu:
   - vmap support for PRIME objects

  tegra:
   - Initial Tegra194 support
   - DMA/IOMMU integration fixes

  msm:
   - a6xx perf improvements + clock prefix
   - GPU preemption optimisations
   - a6xx devfreq support
   - cursor support

  rockchip:
   - PX30 support
   - rgb output interface support

  mediatek:
   - HDMI output support on mt2701 and mt7623

  rcar-du:
   - Interlaced modes on Gen3
   - LVDS on R8A77980
   - D3 and E3 SoC support

  hisilicon:
   - misc fixes

  mxsfb:
   - runtime pm support

  sun4i:
   - R40 TCON support
   - Allwinner A64 support
   - R40 HDMI support

  omapdrm:
   - Driver rework changing display pipeline ordering to use common code
   - DMM memory barrier and irq fixes
   - Errata workarounds

  exynos:
   - out-bridge support for LVDS bridge driver
   - Samsung 16x16 tiled format support
   - Plane alpha and pixel blend mode support

  tilcdc:
   - suspend/resume update

  mali-dp:
   - misc updates"

* tag 'drm-next-2018-10-24' of git://anongit.freedesktop.org/drm/drm: (1382 commits)
  firmware/dmc/icl: Add missing MODULE_FIRMWARE() for Icelake.
  drm/i915/icl: Fix signal_levels
  drm/i915/icl: Fix DDI/TC port clk_off bits
  drm/i915/icl: create function to identify combophy port
  drm/i915/gen9+: Fix initial readout for Y tiled framebuffers
  drm/i915: Large page offsets for pread/pwrite
  drm/i915/selftests: Disable shrinker across mmap-exhaustion
  drm/i915/dp: Link train Fallback on eDP only if fallback link BW can fit panel's native mode
  drm/i915: Fix intel_dp_mst_best_encoder()
  drm/i915: Skip vcpi allocation for MSTB ports that are gone
  drm/i915: Don't unset intel_connector->mst_port
  drm/i915: Only reset seqno if actually idle
  drm/i915: Use the correct crtc when sanitizing plane mapping
  drm/i915: Restore vblank interrupts earlier
  drm/i915: Check fb stride against plane max stride
  drm/amdgpu/vcn:Fix uninitialized symbol error
  drm: panel-orientation-quirks: Add quirk for Acer One 10 (S1003)
  drm/amd/amdgpu: Fix debugfs error handling
  drm/amdgpu: Update gc_9_0 golden settings.
  drm/amd/powerplay: update PPtable with DC BTC and Tvr SocLimit fields
  ...

1 files changed, 287 insertions, 271 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 39bf2ce548c6..1e4dd09a5072 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -62,6 +62,8 @@
 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
+MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
+MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
 
 #define AMDGPU_RESUME_MS                2000
 
@@ -652,71 +654,6 @@ void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
 }
 
 /**
- * amdgpu_device_vram_location - try to find VRAM location
- *
- * @adev: amdgpu device structure holding all necessary informations
- * @mc: memory controller structure holding memory informations
- * @base: base address at which to put VRAM
- *
- * Function will try to place VRAM at base address provided
- * as parameter.
- */
-void amdgpu_device_vram_location(struct amdgpu_device *adev,
-                                 struct amdgpu_gmc *mc, u64 base)
-{
-        uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
-
-        mc->vram_start = base;
-        mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
-        if (limit && limit < mc->real_vram_size)
-                mc->real_vram_size = limit;
-        dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
-                        mc->mc_vram_size >> 20, mc->vram_start,
-                        mc->vram_end, mc->real_vram_size >> 20);
-}
-
-/**
- * amdgpu_device_gart_location - try to find GART location
- *
- * @adev: amdgpu device structure holding all necessary informations
- * @mc: memory controller structure holding memory informations
- *
- * Function will place try to place GART before or after VRAM.
- *
- * If GART size is bigger than space left then we ajust GART size.
- * Thus function will never fails.
- */
-void amdgpu_device_gart_location(struct amdgpu_device *adev,
-                                 struct amdgpu_gmc *mc)
-{
-        u64 size_af, size_bf;
-
-        mc->gart_size += adev->pm.smu_prv_buffer_size;
-
-        size_af = adev->gmc.mc_mask - mc->vram_end;
-        size_bf = mc->vram_start;
-        if (size_bf > size_af) {
-                if (mc->gart_size > size_bf) {
-                        dev_warn(adev->dev, "limiting GART\n");
-                        mc->gart_size = size_bf;
-                }
-                mc->gart_start = 0;
-        } else {
-                if (mc->gart_size > size_af) {
-                        dev_warn(adev->dev, "limiting GART\n");
-                        mc->gart_size = size_af;
-                }
-                /* VCE doesn't like it when BOs cross a 4GB segment, so align
-                 * the GART base on a 4GB boundary as well.
-                 */
-                mc->gart_start = ALIGN(mc->vram_end + 1, 0x100000000ULL);
-        }
-        mc->gart_end = mc->gart_start + mc->gart_size - 1;
-        dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
-                        mc->gart_size >> 20, mc->gart_start, mc->gart_end);
-}
-
-/**
  * amdgpu_device_resize_fb_bar - try to resize FB BAR
  *
  * @adev: amdgpu_device pointer
@@ -1397,7 +1334,12 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
                 chip_name = "vega12";
                 break;
         case CHIP_RAVEN:
-                chip_name = "raven";
+                if (adev->rev_id >= 8)
+                        chip_name = "raven2";
+                else if (adev->pdev->device == 0x15d8)
+                        chip_name = "picasso";
+                else
+                        chip_name = "raven";
                 break;
         }
 
@@ -1551,6 +1493,8 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
         }
 
         adev->powerplay.pp_feature = amdgpu_pp_feature_mask;
+        if (amdgpu_sriov_vf(adev))
+                adev->powerplay.pp_feature &= ~PP_GFXOFF_MASK;
 
         for (i = 0; i < adev->num_ip_blocks; i++) {
                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
@@ -1581,6 +1525,92 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
         return 0;
 }
 
+static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
+{
+        int i, r;
+
+        for (i = 0; i < adev->num_ip_blocks; i++) {
+                if (!adev->ip_blocks[i].status.sw)
+                        continue;
+                if (adev->ip_blocks[i].status.hw)
+                        continue;
+                if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
+                    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
+                        r = adev->ip_blocks[i].version->funcs->hw_init(adev);
+                        if (r) {
+                                DRM_ERROR("hw_init of IP block <%s> failed %d\n",
+                                          adev->ip_blocks[i].version->funcs->name, r);
+                                return r;
+                        }
+                        adev->ip_blocks[i].status.hw = true;
+                }
+        }
+
+        return 0;
+}
+
+static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
+{
+        int i, r;
+
+        for (i = 0; i < adev->num_ip_blocks; i++) {
+                if (!adev->ip_blocks[i].status.sw)
+                        continue;
+                if (adev->ip_blocks[i].status.hw)
+                        continue;
+                r = adev->ip_blocks[i].version->funcs->hw_init(adev);
+                if (r) {
+                        DRM_ERROR("hw_init of IP block <%s> failed %d\n",
+                                  adev->ip_blocks[i].version->funcs->name, r);
+                        return r;
+                }
+                adev->ip_blocks[i].status.hw = true;
+        }
+
+        return 0;
+}
+
+static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
+{
+        int r = 0;
+        int i;
+
+        if (adev->asic_type >= CHIP_VEGA10) {
+                for (i = 0; i < adev->num_ip_blocks; i++) {
+                        if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
+                                if (adev->in_gpu_reset || adev->in_suspend) {
+                                        if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset)
+