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authorMonk Liu <Monk.Liu@amd.com>2017-04-26 00:00:49 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-05-24 17:40:19 -0400
commit2cb681b6e4e317068153e217948d471f3117baee (patch)
tree21d9454ac8e21f94a46327e9fa2ab4cf2b1303d9 /drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
parent17b2e332a277bf8a1314bfa58ac17d38b77d3c14 (diff)
drm/amdgpu:re-write sriov_reinit_early/late (v2)
1,this way we make those routines compatible with the sequence requirment for both Tonga and Vega10 2,ignore PSP hw init when doing TDR, because for SR-IOV device the ucode won't get lost after VF FLR, so no need to invoke PSP doing the ucode reloading again. v2: squash in ARRAY_SIZE fix Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_device.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c63
1 files changed, 39 insertions, 24 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index c20ef335a6ab..9a7c0e4d9cc3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1815,19 +1815,27 @@ static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev)
1815{ 1815{
1816 int i, r; 1816 int i, r;
1817 1817
1818 for (i = 0; i < adev->num_ip_blocks; i++) { 1818 static enum amd_ip_block_type ip_order[] = {
1819 if (!adev->ip_blocks[i].status.valid) 1819 AMD_IP_BLOCK_TYPE_GMC,
1820 continue; 1820 AMD_IP_BLOCK_TYPE_COMMON,
1821 1821 AMD_IP_BLOCK_TYPE_GFXHUB,
1822 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || 1822 AMD_IP_BLOCK_TYPE_MMHUB,
1823 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || 1823 AMD_IP_BLOCK_TYPE_IH,
1824 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) 1824 };
1825 r = adev->ip_blocks[i].version->funcs->hw_init(adev); 1825
1826 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
1827 int j;
1828 struct amdgpu_ip_block *block;
1829
1830 for (j = 0; j < adev->num_ip_blocks; j++) {
1831 block = &adev->ip_blocks[j];
1832
1833 if (block->version->type != ip_order[i] ||
1834 !block->status.valid)
1835 continue;
1826 1836
1827 if (r) { 1837 r = block->version->funcs->hw_init(adev);
1828 DRM_ERROR("resume of IP block <%s> failed %d\n", 1838 DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
1829 adev->ip_blocks[i].version->funcs->name, r);
1830 return r;
1831 } 1839 }
1832 } 1840 }
1833 1841
@@ -1838,20 +1846,27 @@ static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev)
1838{ 1846{
1839 int i, r; 1847 int i, r;
1840 1848
1841 for (i = 0; i < adev->num_ip_blocks; i++) { 1849 static enum amd_ip_block_type ip_order[] = {
1842 if (!adev->ip_blocks[i].status.valid) 1850 AMD_IP_BLOCK_TYPE_SMC,
1843 continue; 1851 AMD_IP_BLOCK_TYPE_DCE,
1852 AMD_IP_BLOCK_TYPE_GFX,
1853 AMD_IP_BLOCK_TYPE_SDMA,
1854 AMD_IP_BLOCK_TYPE_VCE,
1855 };
1844 1856
1845 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || 1857 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
1846 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || 1858 int j;
1847 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ) 1859 struct amdgpu_ip_block *block;
1848 continue;
1849 1860
1850 r = adev->ip_blocks[i].version->funcs->hw_init(adev); 1861 for (j = 0; j < adev->num_ip_blocks; j++) {
1851 if (r) { 1862 block = &adev->ip_blocks[j];
1852 DRM_ERROR("resume of IP block <%s> failed %d\n", 1863
1853 adev->ip_blocks[i].version->funcs->name, r); 1864 if (block->version->type != ip_order[i] ||
1854 return r; 1865 !block->status.valid)
1866 continue;
1867
1868 r = block->version->funcs->hw_init(adev);
1869 DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
1855 } 1870 }
1856 } 1871 }
1857 1872