Merge branch 'next' into for-linus

Prepare input updates for 5.3 merge window.

1 files changed, 33 insertions, 13 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 0acc8dee2cb8..52a5e4fdc95b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -50,7 +50,8 @@ static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
         bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
         p->uf_entry.priority = 0;
         p->uf_entry.tv.bo = &bo->tbo;
-        p->uf_entry.tv.shared = true;
+        /* One for TTM and one for the CS job */
+        p->uf_entry.tv.num_shared = 2;
         p->uf_entry.user_pages = NULL;
 
         drm_gem_object_put_unlocked(gobj);
@@ -213,6 +214,7 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs
                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
+                case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
                         break;
 
                 default:
@@ -598,6 +600,10 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
                         return r;
         }
 
+        /* One for TTM and one for the CS job */
+        amdgpu_bo_list_for_each_entry(e, p->bo_list)
+                e->tv.num_shared = 2;
+
         amdgpu_bo_list_get_list(p->bo_list, &p->validated);
         if (p->bo_list->first_userptr != p->bo_list->num_entries)
                 p->mn = amdgpu_mn_get(p->adev, AMDGPU_MN_TYPE_GFX);
@@ -717,8 +723,14 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
         gws = p->bo_list->gws_obj;
         oa = p->bo_list->oa_obj;
 
-        amdgpu_bo_list_for_each_entry(e, p->bo_list)
-                e->bo_va = amdgpu_vm_bo_find(vm, ttm_to_amdgpu_bo(e->tv.bo));
+        amdgpu_bo_list_for_each_entry(e, p->bo_list) {
+                struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
+
+                /* Make sure we use the exclusive slot for shared BOs */
+                if (bo->prime_shared_count)
+                        e->tv.num_shared = 0;
+                e->bo_va = amdgpu_vm_bo_find(vm, bo);
+        }
 
         if (gds) {
                 p->job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT;
@@ -955,10 +967,6 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
         if (r)
                 return r;
 
-        r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv);
-        if (r)
-                return r;
-
         p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);
 
         if (amdgpu_vm_debug) {
@@ -1083,6 +1091,15 @@ static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
 
                 fence = amdgpu_ctx_get_fence(ctx, entity,
                                              deps[i].handle);
+
+                if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
+                        struct drm_sched_fence *s_fence = to_drm_sched_fence(fence);
+                        struct dma_fence *old = fence;
+
+                        fence = dma_fence_get(&s_fence->scheduled);
+                        dma_fence_put(old);
+                }
+
                 if (IS_ERR(fence)) {
                         r = PTR_ERR(fence);
                         amdgpu_ctx_put(ctx);
@@ -1104,7 +1121,7 @@ static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
 {
         int r;
         struct dma_fence *fence;
-        r = drm_syncobj_find_fence(p->filp, handle, 0, &fence);
+        r = drm_syncobj_find_fence(p->filp, handle, 0, 0, &fence);
         if (r)
                 return r;
 
@@ -1170,7 +1187,8 @@ static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
 
                 chunk = &p->chunks[i];
 
-                if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES) {
+                if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES ||
+                    chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
                         r = amdgpu_cs_process_fence_dep(p, chunk);
                         if (r)
                                 return r;
@@ -1193,7 +1211,7 @@ static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
         int i;
 
         for (i = 0; i < p->num_post_dep_syncobjs; ++i)
-                drm_syncobj_replace_fence(p->post_dep_syncobjs[i], 0, p->fence);
+                drm_syncobj_replace_fence(p->post_dep_syncobjs[i], p->fence);
 }
 
 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
@@ -1260,8 +1278,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
         return 0;
 
 error_abort:
-        dma_fence_put(&job->base.s_fence->finished);
-        job->base.s_fence = NULL;
+        drm_sched_job_cleanup(&job->base);
         amdgpu_mn_unlock(p->mn);
 
 error_unlock:
@@ -1285,7 +1302,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 
         r = amdgpu_cs_parser_init(&parser, data);
         if (r) {
-                DRM_ERROR("Failed to initialize parser !\n");
+                DRM_ERROR("Failed to initialize parser %d!\n", r);
                 goto out;
         }
 
@@ -1422,6 +1439,9 @@ int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
         if (IS_ERR(fence))
                 return PTR_ERR(fence);
 
+        if (!fence)
+                fence = dma_fence_get_stub();
+
         switch (info->in.what) {
         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
                 r = drm_syncobj_create(&syncobj, 0, fence);