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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2018-06-06 11:16:33 -0400 | 
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2018-06-06 11:16:33 -0400 | 
| commit | 135c5504a600ff9b06e321694fbcac78a9530cd4 (patch) | |
| tree | 8d22ed739b0e85954010a964a9aeadf3c692c977 /drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | |
| parent | af6c5d5e01ad9f2c9ca38cccaae6b5d67ddd241f (diff) | |
| parent | 568cf2e6aa0c762f14d2d0d481a006f93c63ab7a (diff) | |
Merge tag 'drm-next-2018-06-06-1' of git://anongit.freedesktop.org/drm/drm
Pull drm updates from Dave Airlie:
 "This starts to support NVIDIA volta hardware with nouveau, and adds
  amdgpu support for the GPU in the Kabylake-G (the intel + radeon
  single package chip), along with some initial Intel icelake enabling.
  Summary:
  New Drivers:
   - v3d - driver for broadcom V3D V3.x+ hardware
   - xen-front - XEN PV display frontend
  core:
   - handle zpos normalization in the core
   - stop looking at legacy pointers in atomic paths
   - improved scheduler documentation
   - improved aspect ratio validation
   - aspect ratio support for 64:27 and 256:135
   - drop unused control node code.
  i915:
   - Icelake (ICL) enabling
   - GuC/HuC refactoring
   - PSR/PSR2 enabling and fixes
   - DPLL management refactoring
   - DP MST fixes
   - NV12 enabling
   - HDCP improvements
   - GEM/Execlist/reset improvements
   - GVT improvements
   - stolen memory first 4k fix
  amdgpu:
   - Vega 20 support
   - VEGAM support (Kabylake-G)
   - preOS scanout buffer reservation
   - power management gfxoff support for raven
   - SR-IOV fixes
   - Vega10 power profiles and clock voltage control
   - scatter/gather display support on CZ/ST
  amdkfd:
   - GFX9 dGPU support
   - userptr memory mapping
  nouveau:
   - major refactoring for Volta GV100 support
  tda998x:
   - HDMI i2c CEC support
  etnaviv:
   - removed unused logging code
   - license text cleanups
   - MMU handling improvements
   - timeout fence fix for 50 days uptime
  tegra:
   - IOMMU support in gr2d/gr3d drivers
   - zpos support
  vc4:
   - syncobj support
   - CTM, plane alpha and async cursor support
  analogix_dp:
   - HPD and aux chan fixes
  sun4i:
   - MIPI DSI support
  tilcdc:
   - clock divider fixes for OMAP-l138 LCDK board
  rcar-du:
   - R8A77965 support
   - dma-buf fences fixes
   - hardware indexed crtc/du group handling
   - generic zplane property support
  atmel-hclcdc:
   - generic zplane property support
  mediatek:
   - use generic video mode function
  exynos:
   - S5PV210 FIMD variant support
   - IPP v2 framework
   - more HW overlays support"
* tag 'drm-next-2018-06-06-1' of git://anongit.freedesktop.org/drm/drm: (1286 commits)
  drm/amdgpu: fix 32-bit build warning
  drm/exynos: fimc: signedness bug in fimc_setup_clocks()
  drm/exynos: scaler: fix static checker warning
  drm/amdgpu: Use dev_info() to report amdkfd is not supported for this ASIC
  drm/amd/display: Remove use of division operator for long longs
  drm/amdgpu: Update GFX info structure to match what vega20 used
  drm/amdgpu/pp: remove duplicate assignment
  drm/sched: add rcu_barrier after entity fini
  drm/amdgpu: move VM BOs on LRU again
  drm/amdgpu: consistenly use VM moved flag
  drm/amdgpu: kmap PDs/PTs in amdgpu_vm_update_directories
  drm/amdgpu: further optimize amdgpu_vm_handle_moved
  drm/amdgpu: cleanup amdgpu_vm_validate_pt_bos v2
  drm/amdgpu: rework VM state machine lock handling v2
  drm/amdgpu: Add runtime VCN PG support
  drm/amdgpu: Enable VCN static PG by default on RV
  drm/amdgpu: Add VCN static PG support on RV
  drm/amdgpu: Enable VCN CG by default on RV
  drm/amdgpu: Add static CG control for VCN on RV
  drm/exynos: Fix default value for zpos plane property
  ...
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 18 | 
1 files changed, 6 insertions, 12 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index dc34b50e6b29..9c1d491d742e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  | |||
| @@ -382,8 +382,7 @@ retry: | |||
| 382 | 382 | ||
| 383 | p->bytes_moved += ctx.bytes_moved; | 383 | p->bytes_moved += ctx.bytes_moved; | 
| 384 | if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size && | 384 | if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size && | 
| 385 | bo->tbo.mem.mem_type == TTM_PL_VRAM && | 385 | amdgpu_bo_in_cpu_visible_vram(bo)) | 
| 386 | bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT) | ||
| 387 | p->bytes_moved_vis += ctx.bytes_moved; | 386 | p->bytes_moved_vis += ctx.bytes_moved; | 
| 388 | 387 | ||
| 389 | if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { | 388 | if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { | 
| @@ -411,7 +410,6 @@ static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p, | |||
| 411 | struct amdgpu_bo_list_entry *candidate = p->evictable; | 410 | struct amdgpu_bo_list_entry *candidate = p->evictable; | 
| 412 | struct amdgpu_bo *bo = candidate->robj; | 411 | struct amdgpu_bo *bo = candidate->robj; | 
| 413 | struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); | 412 | struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); | 
| 414 | u64 initial_bytes_moved, bytes_moved; | ||
| 415 | bool update_bytes_moved_vis; | 413 | bool update_bytes_moved_vis; | 
| 416 | uint32_t other; | 414 | uint32_t other; | 
| 417 | 415 | ||
| @@ -435,18 +433,14 @@ static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p, | |||
| 435 | continue; | 433 | continue; | 
| 436 | 434 | ||
| 437 | /* Good we can try to move this BO somewhere else */ | 435 | /* Good we can try to move this BO somewhere else */ | 
| 438 | amdgpu_ttm_placement_from_domain(bo, other); | ||
| 439 | update_bytes_moved_vis = | 436 | update_bytes_moved_vis = | 
| 440 | adev->gmc.visible_vram_size < adev->gmc.real_vram_size && | 437 | adev->gmc.visible_vram_size < adev->gmc.real_vram_size && | 
| 441 | bo->tbo.mem.mem_type == TTM_PL_VRAM && | 438 | amdgpu_bo_in_cpu_visible_vram(bo); | 
| 442 | bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT; | 439 | amdgpu_ttm_placement_from_domain(bo, other); | 
| 443 | initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); | ||
| 444 | r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); | 440 | r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); | 
| 445 | bytes_moved = atomic64_read(&adev->num_bytes_moved) - | 441 | p->bytes_moved += ctx.bytes_moved; | 
| 446 | initial_bytes_moved; | ||
| 447 | p->bytes_moved += bytes_moved; | ||
| 448 | if (update_bytes_moved_vis) | 442 | if (update_bytes_moved_vis) | 
| 449 | p->bytes_moved_vis += bytes_moved; | 443 | p->bytes_moved_vis += ctx.bytes_moved; | 
| 450 | 444 | ||
| 451 | if (unlikely(r)) | 445 | if (unlikely(r)) | 
| 452 | break; | 446 | break; | 
| @@ -536,7 +530,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, | |||
| 536 | if (p->bo_list) { | 530 | if (p->bo_list) { | 
| 537 | amdgpu_bo_list_get_list(p->bo_list, &p->validated); | 531 | amdgpu_bo_list_get_list(p->bo_list, &p->validated); | 
| 538 | if (p->bo_list->first_userptr != p->bo_list->num_entries) | 532 | if (p->bo_list->first_userptr != p->bo_list->num_entries) | 
| 539 | p->mn = amdgpu_mn_get(p->adev); | 533 | p->mn = amdgpu_mn_get(p->adev, AMDGPU_MN_TYPE_GFX); | 
| 540 | } | 534 | } | 
| 541 | 535 | ||
| 542 | INIT_LIST_HEAD(&duplicates); | 536 | INIT_LIST_HEAD(&duplicates); | 
