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authorRex Zhu <Rex.Zhu@amd.com>2018-03-20 07:19:44 -0400
committerAlex Deucher <alexander.deucher@amd.com>2018-03-21 15:36:58 -0400
commit160b8e75932fd51a49607d32dbfa1d417977b79c (patch)
tree296f80a0248579ad78c29e0c25b1213bb3a49b29 /drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
parent7436854ebd4166a7c4b023031f62f24f1174d2d2 (diff)
drm/amdgpu: Remove wrapper layer of cgs irq handling
v2: add Vega12 support 1. remove struct cgs_os_ops 2. delete cgs_linux.h 3. refine the irq code for vega10, can fix set pp table failed issue. 4. add common smu irq process function Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c111
1 files changed, 0 insertions, 111 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index a8a0fd927da2..71a57b2f7f04 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -28,7 +28,6 @@
28#include <linux/firmware.h> 28#include <linux/firmware.h>
29#include <drm/amdgpu_drm.h> 29#include <drm/amdgpu_drm.h>
30#include "amdgpu.h" 30#include "amdgpu.h"
31#include "cgs_linux.h"
32#include "atom.h" 31#include "atom.h"
33#include "amdgpu_ucode.h" 32#include "amdgpu_ucode.h"
34 33
@@ -182,109 +181,6 @@ static int amdgpu_cgs_atom_exec_cmd_table(struct cgs_device *cgs_device, unsigne
182 adev->mode_info.atom_context, table, args); 181 adev->mode_info.atom_context, table, args);
183} 182}
184 183
185struct cgs_irq_params {
186 unsigned src_id;
187 cgs_irq_source_set_func_t set;
188 cgs_irq_handler_func_t handler;
189 void *private_data;
190};
191
192static int cgs_set_irq_state(struct amdgpu_device *adev,
193 struct amdgpu_irq_src *src,
194 unsigned type,
195 enum amdgpu_interrupt_state state)
196{
197 struct cgs_irq_params *irq_params =
198 (struct cgs_irq_params *)src->data;
199 if (!irq_params)
200 return -EINVAL;
201 if (!irq_params->set)
202 return -EINVAL;
203 return irq_params->set(irq_params->private_data,
204 irq_params->src_id,
205 type,
206 (int)state);
207}
208
209static int cgs_process_irq(struct amdgpu_device *adev,
210 struct amdgpu_irq_src *source,
211 struct amdgpu_iv_entry *entry)
212{
213 struct cgs_irq_params *irq_params =
214 (struct cgs_irq_params *)source->data;
215 if (!irq_params)
216 return -EINVAL;
217 if (!irq_params->handler)
218 return -EINVAL;
219 return irq_params->handler(irq_params->private_data,
220 irq_params->src_id,
221 entry->iv_entry);
222}
223
224static const struct amdgpu_irq_src_funcs cgs_irq_funcs = {
225 .set = cgs_set_irq_state,
226 .process = cgs_process_irq,
227};
228
229static int amdgpu_cgs_add_irq_source(void *cgs_device,
230 unsigned client_id,
231 unsigned src_id,
232 unsigned num_types,
233 cgs_irq_source_set_func_t set,
234 cgs_irq_handler_func_t handler,
235 void *private_data)
236{
237 CGS_FUNC_ADEV;
238 int ret = 0;
239 struct cgs_irq_params *irq_params;
240 struct amdgpu_irq_src *source =
241 kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
242 if (!source)
243 return -ENOMEM;
244 irq_params =
245 kzalloc(sizeof(struct cgs_irq_params), GFP_KERNEL);
246 if (!irq_params) {
247 kfree(source);
248 return -ENOMEM;
249 }
250 source->num_types = num_types;
251 source->funcs = &cgs_irq_funcs;
252 irq_params->src_id = src_id;
253 irq_params->set = set;
254 irq_params->handler = handler;
255 irq_params->private_data = private_data;
256 source->data = (void *)irq_params;
257 ret = amdgpu_irq_add_id(adev, client_id, src_id, source);
258 if (ret) {
259 kfree(irq_params);
260 kfree(source);
261 }
262
263 return ret;
264}
265
266static int amdgpu_cgs_irq_get(void *cgs_device, unsigned client_id,
267 unsigned src_id, unsigned type)
268{
269 CGS_FUNC_ADEV;
270
271 if (!adev->irq.client[client_id].sources)
272 return -EINVAL;
273
274 return amdgpu_irq_get(adev, adev->irq.client[client_id].sources[src_id], type);
275}
276
277static int amdgpu_cgs_irq_put(void *cgs_device, unsigned client_id,
278 unsigned src_id, unsigned type)
279{
280 CGS_FUNC_ADEV;
281
282 if (!adev->irq.client[client_id].sources)
283 return -EINVAL;
284
285 return amdgpu_irq_put(adev, adev->irq.client[client_id].sources[src_id], type);
286}
287
288static int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device, 184static int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device,
289 enum amd_ip_block_type block_type, 185 enum amd_ip_block_type block_type,
290 enum amd_clockgating_state state) 186 enum amd_clockgating_state state)
@@ -795,12 +691,6 @@ static const struct cgs_ops amdgpu_cgs_ops = {
795 .lock_grbm_idx = amdgpu_cgs_lock_grbm_idx, 691 .lock_grbm_idx = amdgpu_cgs_lock_grbm_idx,
796}; 692};
797 693
798static const struct cgs_os_ops amdgpu_cgs_os_ops = {
799 .add_irq_source = amdgpu_cgs_add_irq_source,
800 .irq_get = amdgpu_cgs_irq_get,
801 .irq_put = amdgpu_cgs_irq_put
802};
803
804struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev) 694struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)
805{ 695{
806 struct amdgpu_cgs_device *cgs_device = 696 struct amdgpu_cgs_device *cgs_device =
@@ -812,7 +702,6 @@ struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)
812 } 702 }
813 703
814 cgs_device->base.ops = &amdgpu_cgs_ops; 704 cgs_device->base.ops = &amdgpu_cgs_ops;
815 cgs_device->base.os_ops = &amdgpu_cgs_os_ops;
816 cgs_device->adev = adev; 705 cgs_device->adev = adev;
817 706
818 return (struct cgs_device *)cgs_device; 707 return (struct cgs_device *)cgs_device;