Merge branch 'next' into for-linus

Prepare second round of input updates for 5.3 merge window.

1 files changed, 66 insertions, 7 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index b61e1dc61b4c..f96d75c6e099 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -28,8 +28,6 @@
 #include "atom.h"
 #include "atombios.h"
 
-#define get_index_into_master_table(master_table, table_name) (offsetof(struct master_table, table_name) / sizeof(uint16_t))
-
 bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev)
 {
         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
@@ -238,10 +236,71 @@ int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev)
         return 0;
 }
 
+/*
+ * Return true if vbios enabled ecc by default, if umc info table is available
+ * or false if ecc is not enabled or umc info table is not available
+ */
+bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
+{
+        struct amdgpu_mode_info *mode_info = &adev->mode_info;
+        int index;
+        u16 data_offset, size;
+        union umc_info *umc_info;
+        u8 frev, crev;
+        bool ecc_default_enabled = false;
+
+        index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+                        umc_info);
+
+        if (amdgpu_atom_parse_data_header(mode_info->atom_context,
+                                index, &size, &frev, &crev, &data_offset)) {
+                /* support umc_info 3.1+ */
+                if ((frev == 3 && crev >= 1) || (frev > 3)) {
+                        umc_info = (union umc_info *)
+                                (mode_info->atom_context->bios + data_offset);
+                        ecc_default_enabled =
+                                (le32_to_cpu(umc_info->v31.umc_config) &
+                                 UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
+                }
+        }
+
+        return ecc_default_enabled;
+}
+
 union firmware_info {
         struct atom_firmware_info_v3_1 v31;
 };
 
+/*
+ * Return true if vbios supports sram ecc or false if not
+ */
+bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev)
+{
+        struct amdgpu_mode_info *mode_info = &adev->mode_info;
+        int index;
+        u16 data_offset, size;
+        union firmware_info *firmware_info;
+        u8 frev, crev;
+        bool sram_ecc_supported = false;
+
+        index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+                        firmwareinfo);
+
+        if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
+                                index, &size, &frev, &crev, &data_offset)) {
+                /* support firmware_info 3.1 + */
+                if ((frev == 3 && crev >=1) || (frev > 3)) {
+                        firmware_info = (union firmware_info *)
+                                (mode_info->atom_context->bios + data_offset);
+                        sram_ecc_supported =
+                                (le32_to_cpu(firmware_info->v31.firmware_capability) &
+                                 ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false;
+                }
+        }
+
+        return sram_ecc_supported;
+}
+
 union smu_info {
         struct atom_smu_info_v3_1 v31;
 };
@@ -346,11 +405,11 @@ int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
                         (mode_info->atom_context->bios + data_offset);
                 switch (crev) {
                 case 4:
-                        adev->gfx.config.max_shader_engines = gfx_info->v24.gc_num_se;
-                        adev->gfx.config.max_cu_per_sh = gfx_info->v24.gc_num_cu_per_sh;
-                        adev->gfx.config.max_sh_per_se = gfx_info->v24.gc_num_sh_per_se;
-                        adev->gfx.config.max_backends_per_se = gfx_info->v24.gc_num_rb_per_se;
-                        adev->gfx.config.max_texture_channel_caches = gfx_info->v24.gc_num_tccs;
+                        adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines;
+                        adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh;
+                        adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se;
+                        adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se;
+                        adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches;
                         adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
                         adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
                         adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;