Merge branch 'drm-next-4.17' of git://people.freedesktop.org/~agd5f/linux into drm-next

- Continued cleanup and restructuring of powerplay
- Fetch VRAM type from vbios rather than hardcoding for SOC15 asics
- Allow ttm to drop its backing store when drivers don't need it
- DC bandwidth calc updates
- Enable DC backlight control pre-DCE11 asics
- Enable DC on all supported asics
- DC Fixes for planes due to the way our hw is ordered vs what drm expects
- DC CTM/regamma fixes
- Misc cleanup and bug fixes

* 'drm-next-4.17' of git://people.freedesktop.org/~agd5f/linux: (89 commits)
  amdgpu/dm: Default PRE_VEGA ASIC support to 'y'
  drm/amd/pp: Remove the cgs wrapper for notify smu version on APU
  drm/amd/display: fix dereferencing possible ERR_PTR()
  drm/amd/display: Refine disable VGA
  drm/amdgpu: Improve documentation of bo_ptr in amdgpu_bo_create_kernel
  drm/radeon: Don't turn off DP sink when disconnected
  drm/amd/pp: Rename file name cz_* to smu8_*
  drm/amd/pp: Replace function/struct name cz_* with smu8_*
  drm/amd/pp: Remove unneeded void * casts in cz_hwmgr.c/cz_smumgr.c
  drm/amd/pp: Mv cz uvd/vce pg/dpm functions to cz_hwmgr.c
  drm/amd/pp: Remove dead header file pp_asicblocks.h
  drm/amd/pp: Delete dead code on cz_clockpowergating.c
  drm/amdgpu: Call amdgpu_ucode_fini_bo in amd_powerplay.c
  drm/amdgpu: Remove wrapper layer of smu ip functions
  drm/amdgpu: Don't compared ip_block_type with ip_block_index
  drm/amdgpu: Plus NULL function pointer check
  drm/amd/pp: Move helper functions to smu_help.c
  drm/amd/pp: Replace rv_* with smu10_*
  drm/amd/pp: Fix function parameter not correct
  drm/amd/pp: Add rv_copy_table_from/to_smc to smu backend function table
  ...

1 files changed, 91 insertions, 4 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index ff8efd0f8fd5..a0f48cb9b8f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -114,6 +114,9 @@ union igp_info {
         struct atom_integrated_system_info_v1_11 v11;
 };
 
+union umc_info {
+        struct atom_umc_info_v3_1 v31;
+};
 /*
  * Return vram width from integrated system info table, if available,
  * or 0 if not.
@@ -143,6 +146,94 @@ int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev)
         return 0;
 }
 
+static int convert_atom_mem_type_to_vram_type (struct amdgpu_device *adev,
+                                               int atom_mem_type)
+{
+        int vram_type;
+
+        if (adev->flags & AMD_IS_APU) {
+                switch (atom_mem_type) {
+                case Ddr2MemType:
+                case LpDdr2MemType:
+                        vram_type = AMDGPU_VRAM_TYPE_DDR2;
+                        break;
+                case Ddr3MemType:
+                case LpDdr3MemType:
+                        vram_type = AMDGPU_VRAM_TYPE_DDR3;
+                        break;
+                case Ddr4MemType:
+                case LpDdr4MemType:
+                        vram_type = AMDGPU_VRAM_TYPE_DDR4;
+                        break;
+                default:
+                        vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
+                        break;
+                }
+        } else {
+                switch (atom_mem_type) {
+                case ATOM_DGPU_VRAM_TYPE_GDDR5:
+                        vram_type = AMDGPU_VRAM_TYPE_GDDR5;
+                        break;
+                case ATOM_DGPU_VRAM_TYPE_HBM:
+                        vram_type = AMDGPU_VRAM_TYPE_HBM;
+                        break;
+                default:
+                        vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
+                        break;
+                }
+        }
+
+        return vram_type;
+}
+/*
+ * Return vram type from either integrated system info table
+ * or umc info table, if available, or 0 (TYPE_UNKNOWN) if not
+ */
+int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev)
+{
+        struct amdgpu_mode_info *mode_info = &adev->mode_info;
+        int index;
+        u16 data_offset, size;
+        union igp_info *igp_info;
+        union umc_info *umc_info;
+        u8 frev, crev;
+        u8 mem_type;
+
+        if (adev->flags & AMD_IS_APU)
+                index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+                                                    integratedsysteminfo);
+        else
+                index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+                                                    umc_info);
+        if (amdgpu_atom_parse_data_header(mode_info->atom_context,
+                                          index, &size,
+                                          &frev, &crev, &data_offset)) {
+                if (adev->flags & AMD_IS_APU) {
+                        igp_info = (union igp_info *)
+                                (mode_info->atom_context->bios + data_offset);
+                        switch (crev) {
+                        case 11:
+                                mem_type = igp_info->v11.memorytype;
+                                return convert_atom_mem_type_to_vram_type(adev, mem_type);
+                        default:
+                                return 0;
+                        }
+                } else {
+                        umc_info = (union umc_info *)
+                                (mode_info->atom_context->bios + data_offset);
+                        switch (crev) {
+                        case 1:
+                                mem_type = umc_info->v31.vram_type;
+                                return convert_atom_mem_type_to_vram_type(adev, mem_type);
+                        default:
+                                return 0;
+                        }
+                }
+        }
+
+        return 0;
+}
+
 union firmware_info {
         struct atom_firmware_info_v3_1 v31;
 };
@@ -151,10 +242,6 @@ union smu_info {
         struct atom_smu_info_v3_1 v31;
 };
 
-union umc_info {
-        struct atom_umc_info_v3_1 v31;
-};
-
 int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
 {
         struct amdgpu_mode_info *mode_info = &adev->mode_info;