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authorOak Zeng <ozeng@amd.com>2018-11-23 14:48:27 -0500
committerAlex Deucher <alexander.deucher@amd.com>2018-11-28 15:55:33 -0500
commitcde577bd116e14174652c5abe1f881381c9a131e (patch)
tree16f46dca62409c689a4de00652592b66da356f1a /drivers/gpu/drm/amd/amdgpu/amdgpu.h
parent9564f1928ed29b093bb997df9573e8edae61983d (diff)
drm/amdgpu: Move doorbell structures to seperate file
Move doorbell structures, enum definitions and helper functions from amdgpu.h to amdgpu_doorbell.h. No functional change Signed-off-by: Oak Zeng <ozeng@amd.com> Proposed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu.h')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h221
1 files changed, 1 insertions, 220 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 9ec5f5a6ac39..78fe21b88a00 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -81,6 +81,7 @@
81#include "amdgpu_job.h" 81#include "amdgpu_job.h"
82#include "amdgpu_bo_list.h" 82#include "amdgpu_bo_list.h"
83#include "amdgpu_gem.h" 83#include "amdgpu_gem.h"
84#include "amdgpu_doorbell.h"
84 85
85#define MAX_GPU_INSTANCE 16 86#define MAX_GPU_INSTANCE 16
86 87
@@ -361,167 +362,6 @@ int amdgpu_fence_slab_init(void);
361void amdgpu_fence_slab_fini(void); 362void amdgpu_fence_slab_fini(void);
362 363
363/* 364/*
364 * GPU doorbell structures, functions & helpers
365 */
366typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
367{
368 AMDGPU_DOORBELL_KIQ = 0x000,
369 AMDGPU_DOORBELL_HIQ = 0x001,
370 AMDGPU_DOORBELL_DIQ = 0x002,
371 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
372 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
373 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
374 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
375 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
376 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
377 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
378 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
379 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
380 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
381 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
382 AMDGPU_DOORBELL_IH = 0x1E8,
383 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
384 AMDGPU_DOORBELL_INVALID = 0xFFFF
385} AMDGPU_DOORBELL_ASSIGNMENT;
386
387struct amdgpu_doorbell {
388 /* doorbell mmio */
389 resource_size_t base;
390 resource_size_t size;
391 u32 __iomem *ptr;
392 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
393};
394
395typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT
396{
397 /* Compute + GFX: 0~255 */
398 AMDGPU_VEGA20_DOORBELL_KIQ = 0x000,
399 AMDGPU_VEGA20_DOORBELL_HIQ = 0x001,
400 AMDGPU_VEGA20_DOORBELL_DIQ = 0x002,
401 AMDGPU_VEGA20_DOORBELL_MEC_RING0 = 0x003,
402 AMDGPU_VEGA20_DOORBELL_MEC_RING1 = 0x004,
403 AMDGPU_VEGA20_DOORBELL_MEC_RING2 = 0x005,
404 AMDGPU_VEGA20_DOORBELL_MEC_RING3 = 0x006,
405 AMDGPU_VEGA20_DOORBELL_MEC_RING4 = 0x007,
406 AMDGPU_VEGA20_DOORBELL_MEC_RING5 = 0x008,
407 AMDGPU_VEGA20_DOORBELL_MEC_RING6 = 0x009,
408 AMDGPU_VEGA20_DOORBELL_MEC_RING7 = 0x00A,
409 AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = 0x00B,
410 AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = 0x08A,
411 AMDGPU_VEGA20_DOORBELL_GFX_RING0 = 0x08B,
412 /* SDMA:256~335*/
413 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 = 0x100,
414 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 = 0x10A,
415 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 = 0x114,
416 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 = 0x11E,
417 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 = 0x128,
418 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 = 0x132,
419 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 = 0x13C,
420 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 = 0x146,
421 /* IH: 376~391 */
422 AMDGPU_VEGA20_DOORBELL_IH = 0x178,
423 /* MMSCH: 392~407
424 * overlap the doorbell assignment with VCN as they are mutually exclusive
425 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
426 */
427 AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
428 AMDGPU_VEGA20_DOORBELL64_VCN2_3 = 0x189,
429 AMDGPU_VEGA20_DOORBELL64_VCN4_5 = 0x18A,
430 AMDGPU_VEGA20_DOORBELL64_VCN6_7 = 0x18B,
431
432 AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = 0x188,
433 AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = 0x189,
434 AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = 0x18A,
435 AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 = 0x18B,
436
437 AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 = 0x18C,
438 AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 0x18D,
439 AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 0x18E,
440 AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 0x18F,
441 AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 0x18F,
442 AMDGPU_VEGA20_DOORBELL_INVALID = 0xFFFF
443} AMDGPU_VEGA20_DOORBELL_ASSIGNMENT;
444
445/*
446 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
447 */
448typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
449{
450 /*
451 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
452 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
453 * Compute related doorbells are allocated from 0x00 to 0x8a
454 */
455
456
457 /* kernel scheduling */
458 AMDGPU_DOORBELL64_KIQ = 0x00,
459
460 /* HSA interface queue and debug queue */
461 AMDGPU_DOORBELL64_HIQ = 0x01,
462 AMDGPU_DOORBELL64_DIQ = 0x02,
463
464 /* Compute engines */
465 AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
466 AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
467 AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
468 AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
469 AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
470 AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
471 AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
472 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
473
474 /* User queue doorbell range (128 doorbells) */
475 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
476 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
477
478 /* Graphics engine */
479 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
480
481 /*
482 * Other graphics doorbells can be allocated here: from 0x8c to 0xdf
483 * Graphics voltage island aperture 1
484 * default non-graphics QWORD index is 0xe0 - 0xFF inclusive
485 */
486
487 /* For vega10 sriov, the sdma doorbell must be fixed as follow
488 * to keep the same setting with host driver, or it will
489 * happen conflicts
490 */
491 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
492 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
493 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
494 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
495
496 /* Interrupt handler */
497 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
498 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
499 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
500
501 /* VCN engine use 32 bits doorbell */
502 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
503 AMDGPU_DOORBELL64_VCN2_3 = 0xF9,
504 AMDGPU_DOORBELL64_VCN4_5 = 0xFA,
505 AMDGPU_DOORBELL64_VCN6_7 = 0xFB,
506
507 /* overlap the doorbell assignment with VCN as they are mutually exclusive
508 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
509 */
510 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8,
511 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9,
512 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA,
513 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB,
514
515 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC,
516 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD,
517 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE,
518 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF,
519
520 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
521 AMDGPU_DOORBELL64_INVALID = 0xFFFF
522} AMDGPU_DOORBELL64_ASSIGNMENT;
523
524/*
525 * IRQS. 365 * IRQS.
526 */ 366 */
527 367
@@ -856,55 +696,6 @@ struct amd_powerplay {
856 uint32_t pp_feature; 696 uint32_t pp_feature;
857}; 697};
858 698
859/* Reserved doorbells for amdgpu (including multimedia).
860 * KFD can use all the rest in the 2M doorbell bar.
861 * For asic before vega10, doorbell is 32-bit, so the
862 * index/offset is in dword. For vega10 and after, doorbell
863 * can be 64-bit, so the index defined is in qword.
864 */
865struct amdgpu_doorbell_index {
866 uint32_t kiq;
867 uint32_t mec_ring0;
868 uint32_t mec_ring1;
869 uint32_t mec_ring2;
870 uint32_t mec_ring3;
871 uint32_t mec_ring4;
872 uint32_t mec_ring5;
873 uint32_t mec_ring6;
874 uint32_t mec_ring7;
875 uint32_t userqueue_start;
876 uint32_t userqueue_end;
877 uint32_t gfx_ring0;
878 uint32_t sdma_engine0;
879 uint32_t sdma_engine1;
880 uint32_t sdma_engine2;
881 uint32_t sdma_engine3;
882 uint32_t sdma_engine4;
883 uint32_t sdma_engine5;
884 uint32_t sdma_engine6;
885 uint32_t sdma_engine7;
886 uint32_t ih;
887 union {
888 struct {
889 uint32_t vcn_ring0_1;
890 uint32_t vcn_ring2_3;
891 uint32_t vcn_ring4_5;
892 uint32_t vcn_ring6_7;
893 } vcn;
894 struct {
895 uint32_t uvd_ring0_1;
896 uint32_t uvd_ring2_3;
897 uint32_t uvd_ring4_5;
898 uint32_t uvd_ring6_7;
899 uint32_t vce_ring0_1;
900 uint32_t vce_ring2_3;
901 uint32_t vce_ring4_5;
902 uint32_t vce_ring6_7;
903 } uvd_vce;
904 };
905 uint32_t max_assignment;
906};
907
908#define AMDGPU_RESET_MAGIC_NUM 64 699#define AMDGPU_RESET_MAGIC_NUM 64
909struct amdgpu_device { 700struct amdgpu_device {
910 struct device *dev; 701 struct device *dev;
@@ -1143,11 +934,6 @@ uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1143u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 934u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1144void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 935void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1145 936
1146u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
1147void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
1148u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
1149void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
1150
1151bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 937bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1152bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 938bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1153 939
@@ -1209,11 +995,6 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
1209#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 995#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1210#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 996#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1211 997
1212#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
1213#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
1214#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
1215#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
1216
1217#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 998#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1218#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 999#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1219 1000
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