aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/amdgpu/amdgpu.h
diff options
context:
space:
mode:
authorOak Zeng <ozeng@amd.com>2018-11-19 16:59:53 -0500
committerAlex Deucher <alexander.deucher@amd.com>2018-11-28 15:55:32 -0500
commitc93aa77586c2ffe328cca32b40fc988bde8318b2 (patch)
treea6e52fb5a450268c336c5a13fd04aaef6109ae06 /drivers/gpu/drm/amd/amdgpu/amdgpu.h
parent4e2c1ac2027d1ad99109b676450db8759779222c (diff)
drm/amdgpu: Doorbell layout for vega20 and future asic
This introduces new doorbell layout for vega20 and future asics v2: Use enum definition instead of hardcoded value Signed-off-by: Oak Zeng <ozeng@amd.com> Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu.h')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h50
1 files changed, 50 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 7e9d9b97183a..9ec5f5a6ac39 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -392,6 +392,56 @@ struct amdgpu_doorbell {
392 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 392 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
393}; 393};
394 394
395typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT
396{
397 /* Compute + GFX: 0~255 */
398 AMDGPU_VEGA20_DOORBELL_KIQ = 0x000,
399 AMDGPU_VEGA20_DOORBELL_HIQ = 0x001,
400 AMDGPU_VEGA20_DOORBELL_DIQ = 0x002,
401 AMDGPU_VEGA20_DOORBELL_MEC_RING0 = 0x003,
402 AMDGPU_VEGA20_DOORBELL_MEC_RING1 = 0x004,
403 AMDGPU_VEGA20_DOORBELL_MEC_RING2 = 0x005,
404 AMDGPU_VEGA20_DOORBELL_MEC_RING3 = 0x006,
405 AMDGPU_VEGA20_DOORBELL_MEC_RING4 = 0x007,
406 AMDGPU_VEGA20_DOORBELL_MEC_RING5 = 0x008,
407 AMDGPU_VEGA20_DOORBELL_MEC_RING6 = 0x009,
408 AMDGPU_VEGA20_DOORBELL_MEC_RING7 = 0x00A,
409 AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = 0x00B,
410 AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = 0x08A,
411 AMDGPU_VEGA20_DOORBELL_GFX_RING0 = 0x08B,
412 /* SDMA:256~335*/
413 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 = 0x100,
414 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 = 0x10A,
415 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 = 0x114,
416 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 = 0x11E,
417 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 = 0x128,
418 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 = 0x132,
419 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 = 0x13C,
420 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 = 0x146,
421 /* IH: 376~391 */
422 AMDGPU_VEGA20_DOORBELL_IH = 0x178,
423 /* MMSCH: 392~407
424 * overlap the doorbell assignment with VCN as they are mutually exclusive
425 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
426 */
427 AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
428 AMDGPU_VEGA20_DOORBELL64_VCN2_3 = 0x189,
429 AMDGPU_VEGA20_DOORBELL64_VCN4_5 = 0x18A,
430 AMDGPU_VEGA20_DOORBELL64_VCN6_7 = 0x18B,
431
432 AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = 0x188,
433 AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = 0x189,
434 AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = 0x18A,
435 AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 = 0x18B,
436
437 AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 = 0x18C,
438 AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 0x18D,
439 AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 0x18E,
440 AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 0x18F,
441 AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 0x18F,
442 AMDGPU_VEGA20_DOORBELL_INVALID = 0xFFFF
443} AMDGPU_VEGA20_DOORBELL_ASSIGNMENT;
444
395/* 445/*
396 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space 446 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
397 */ 447 */