drm/amdgpu/sriov: Correct the setting about sdma doorbell offset of Vega10

Correct the format

For vega10 sriov, the sdma doorbell must be fixed as follow to keep the
same setting with host driver, or it will happen conflicts.

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 9 insertions, 0 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 01a23157f6f5..c05b39438663 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -420,6 +420,15 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
         AMDGPU_DOORBELL64_sDMA_ENGINE1            = 0xE8,
         AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xE9,
 
+        /* For vega10 sriov, the sdma doorbell must be fixed as follow
+         * to keep the same setting with host driver, or it will
+         * happen conflicts
+         */
+        AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0            = 0xF0,
+        AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE0     = 0xF1,
+        AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1            = 0xF2,
+        AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xF3,
+
         /* Interrupt handler */
         AMDGPU_DOORBELL64_IH                      = 0xF4,  /* For legacy interrupt ring buffer */
         AMDGPU_DOORBELL64_IH_RING1                = 0xF5,  /* For page migration request log */