diff options
author | Dave Airlie <airlied@redhat.com> | 2016-09-27 21:27:05 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2016-09-27 21:27:05 -0400 |
commit | 9f4ef05bcdcfdf911b056b471dd3c6a4f331b644 (patch) | |
tree | ba8dfba87b4fe5295598f5438881822b6d3395f0 /drivers/gpu/drm/amd/amdgpu/amdgpu.h | |
parent | 81c5d6aa3983662b6b48b504fe3a0a4c640f6a84 (diff) | |
parent | beb86f29c9c7f2d04f9a42c4c61cc469c3689779 (diff) |
Merge branch 'drm-next-4.9' of git://people.freedesktop.org/~agd5f/linux into drm-next
Last set of radeon and amdgpu changes for 4.9. This is
mostly just the powerplay cleanup for dGPUs. Beyond that,
just misc code cleanups and bug fixes.
* 'drm-next-4.9' of git://people.freedesktop.org/~agd5f/linux: (49 commits)
drm/amd/amdgpu: Clean up afmt allocation in DCEv6. (v2)
drm/amd/amdgpu: Remove division from vblank_wait
drm/radeon/atif: Send a hotplug event when we get dgpu display request
drm/radeon/atpx: check for ATIF dGPU wake for display events support
drm/amdgpu/atif: Send a hotplug event when we get dgpu display request
drm/amdgpu/atpx: check for ATIF dGPU wake for display events support
drm/amdgpu: bump version for new vce packet support
drm/amdgpu/vce: allow the clock table packet
drm/amdgpu:cleanup virt related define
drm/amdgpu: use powerplay module for dgpu in Vi.
drm/amdgpu: set gfx clock gating for tonga/polaris.
drm/amdgpu: set system clock gating for tonga/polaris.
drm/amd/powerplay: export function to help to set cg by smu.
drm/amdgpu: avoid out of bounds access on array interrupt_status_offsets
drm/amdgpu: mark symbols static where possible
drm/amdgpu: remove unused functions
drm/amd/powerplay: Replace per-asic print_performance with generic
drm/radeon: narrow asic_init for virtualization
drm/amdgpu:add fw version entry to info
drm/amdgpu:determine if vPost is needed indeed
...
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu.h')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu.h | 28 |
1 files changed, 10 insertions, 18 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index ee45d9f7f3dc..9d79e4ba0213 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h | |||
@@ -57,6 +57,7 @@ | |||
57 | #include "amdgpu_acp.h" | 57 | #include "amdgpu_acp.h" |
58 | 58 | ||
59 | #include "gpu_scheduler.h" | 59 | #include "gpu_scheduler.h" |
60 | #include "amdgpu_virt.h" | ||
60 | 61 | ||
61 | /* | 62 | /* |
62 | * Modules parameters. | 63 | * Modules parameters. |
@@ -1827,6 +1828,7 @@ struct amdgpu_asic_funcs { | |||
1827 | bool (*read_disabled_bios)(struct amdgpu_device *adev); | 1828 | bool (*read_disabled_bios)(struct amdgpu_device *adev); |
1828 | bool (*read_bios_from_rom)(struct amdgpu_device *adev, | 1829 | bool (*read_bios_from_rom)(struct amdgpu_device *adev, |
1829 | u8 *bios, u32 length_bytes); | 1830 | u8 *bios, u32 length_bytes); |
1831 | void (*detect_hw_virtualization) (struct amdgpu_device *adev); | ||
1830 | int (*read_register)(struct amdgpu_device *adev, u32 se_num, | 1832 | int (*read_register)(struct amdgpu_device *adev, u32 se_num, |
1831 | u32 sh_num, u32 reg_offset, u32 *value); | 1833 | u32 sh_num, u32 reg_offset, u32 *value); |
1832 | void (*set_vga_state)(struct amdgpu_device *adev, bool state); | 1834 | void (*set_vga_state)(struct amdgpu_device *adev, bool state); |
@@ -1836,8 +1838,6 @@ struct amdgpu_asic_funcs { | |||
1836 | /* MM block clocks */ | 1838 | /* MM block clocks */ |
1837 | int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); | 1839 | int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); |
1838 | int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); | 1840 | int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); |
1839 | /* query virtual capabilities */ | ||
1840 | u32 (*get_virtual_caps)(struct amdgpu_device *adev); | ||
1841 | /* static power management */ | 1841 | /* static power management */ |
1842 | int (*get_pcie_lanes)(struct amdgpu_device *adev); | 1842 | int (*get_pcie_lanes)(struct amdgpu_device *adev); |
1843 | void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); | 1843 | void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); |
@@ -1933,16 +1933,6 @@ struct amdgpu_atcs { | |||
1933 | struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); | 1933 | struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); |
1934 | void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); | 1934 | void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); |
1935 | 1935 | ||
1936 | |||
1937 | /* GPU virtualization */ | ||
1938 | #define AMDGPU_VIRT_CAPS_SRIOV_EN (1 << 0) | ||
1939 | #define AMDGPU_VIRT_CAPS_IS_VF (1 << 1) | ||
1940 | struct amdgpu_virtualization { | ||
1941 | bool supports_sr_iov; | ||
1942 | bool is_virtual; | ||
1943 | u32 caps; | ||
1944 | }; | ||
1945 | |||
1946 | /* | 1936 | /* |
1947 | * Core structure, functions and helpers. | 1937 | * Core structure, functions and helpers. |
1948 | */ | 1938 | */ |
@@ -2260,12 +2250,12 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) | |||
2260 | #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) | 2250 | #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) |
2261 | #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) | 2251 | #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) |
2262 | #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) | 2252 | #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) |
2263 | #define amdgpu_asic_get_virtual_caps(adev) ((adev)->asic_funcs->get_virtual_caps((adev))) | ||
2264 | #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) | 2253 | #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) |
2265 | #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) | 2254 | #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) |
2266 | #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) | 2255 | #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) |
2267 | #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) | 2256 | #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) |
2268 | #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) | 2257 | #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) |
2258 | #define amdgpu_asic_detect_hw_virtualization(adev) (adev)->asic_funcs->detect_hw_virtualization((adev)) | ||
2269 | #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) | 2259 | #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) |
2270 | #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) | 2260 | #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) |
2271 | #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) | 2261 | #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) |
@@ -2323,6 +2313,11 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) | |||
2323 | #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) | 2313 | #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) |
2324 | #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) | 2314 | #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) |
2325 | 2315 | ||
2316 | #define amdgpu_dpm_read_sensor(adev, idx, value) \ | ||
2317 | ((adev)->pp_enabled ? \ | ||
2318 | (adev)->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, (idx), (value)) : \ | ||
2319 | -EINVAL) | ||
2320 | |||
2326 | #define amdgpu_dpm_get_temperature(adev) \ | 2321 | #define amdgpu_dpm_get_temperature(adev) \ |
2327 | ((adev)->pp_enabled ? \ | 2322 | ((adev)->pp_enabled ? \ |
2328 | (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \ | 2323 | (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \ |
@@ -2374,11 +2369,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) | |||
2374 | (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \ | 2369 | (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \ |
2375 | (adev)->pm.funcs->powergate_vce((adev), (g))) | 2370 | (adev)->pm.funcs->powergate_vce((adev), (g))) |
2376 | 2371 | ||
2377 | #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \ | ||
2378 | ((adev)->pp_enabled ? \ | ||
2379 | (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \ | ||
2380 | (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))) | ||
2381 | |||
2382 | #define amdgpu_dpm_get_current_power_state(adev) \ | 2372 | #define amdgpu_dpm_get_current_power_state(adev) \ |
2383 | (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle) | 2373 | (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle) |
2384 | 2374 | ||
@@ -2460,11 +2450,13 @@ void amdgpu_register_atpx_handler(void); | |||
2460 | void amdgpu_unregister_atpx_handler(void); | 2450 | void amdgpu_unregister_atpx_handler(void); |
2461 | bool amdgpu_has_atpx_dgpu_power_cntl(void); | 2451 | bool amdgpu_has_atpx_dgpu_power_cntl(void); |
2462 | bool amdgpu_is_atpx_hybrid(void); | 2452 | bool amdgpu_is_atpx_hybrid(void); |
2453 | bool amdgpu_atpx_dgpu_req_power_for_displays(void); | ||
2463 | #else | 2454 | #else |
2464 | static inline void amdgpu_register_atpx_handler(void) {} | 2455 | static inline void amdgpu_register_atpx_handler(void) {} |
2465 | static inline void amdgpu_unregister_atpx_handler(void) {} | 2456 | static inline void amdgpu_unregister_atpx_handler(void) {} |
2466 | static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } | 2457 | static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } |
2467 | static inline bool amdgpu_is_atpx_hybrid(void) { return false; } | 2458 | static inline bool amdgpu_is_atpx_hybrid(void) { return false; } |
2459 | static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } | ||
2468 | #endif | 2460 | #endif |
2469 | 2461 | ||
2470 | /* | 2462 | /* |