drm/amdgpu: Add parsing SQ_EDC_INFO to SQ IH v3.

Access to SQ_EDC_INFO requires selecting register instance and
hence mutex lock when accessing GRBM_GFX_INDEX for which a work
is schedueled from IH. But SQ interrupt can be raised on many instances
at once which means queuing work will usually succeed for the first one
but fail for the rest since the work takes time to process. To avoid
losing info about other interrupt instances call the parsing function
directly from high IRQ when current work hasn't finished and avoid
accessing SQ_EDC_INFO in that case.

v2:
Simplify high IRQ and BH handlers synchronization using work_pending.
Remove {READ,WRITE}_ONCE notations since smp_{r,w}mb are implicit
compiler barriers.

v3:
Remove exlicit memory barriers as scedule_work has r/w barriers.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 7 insertions, 0 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 71b9b861f60e..fb17838114c3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -930,6 +930,11 @@ struct amdgpu_ngg {
         bool                    init;
 };
 
+struct sq_work {
+        struct work_struct      work;
+        unsigned ih_data;
+};
+
 struct amdgpu_gfx {
         struct mutex                    gpu_clock_mutex;
         struct amdgpu_gfx_config        config;
@@ -970,6 +975,8 @@ struct amdgpu_gfx {
         struct amdgpu_irq_src           priv_inst_irq;
         struct amdgpu_irq_src           cp_ecc_error_irq;
         struct amdgpu_irq_src           sq_irq;
+        struct sq_work                  sq_work;
+
         /* gfx status */
         uint32_t                        gfx_current_status;
         /* ce ram size*/