diff options
author | Chunming Zhou <david1.zhou@amd.com> | 2015-06-01 02:35:03 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2015-06-05 11:02:06 -0400 |
commit | 890ee23fc60193d7c2bca17e099569f1510b3053 (patch) | |
tree | d62da1cfdac0561c2a536fe1c3d0abe7162b3360 /drivers/gpu/drm/amd/amdgpu/amdgpu.h | |
parent | 9298e52f8b51d1e4acd68f502832f3a97f8cf892 (diff) |
drm/amdgpu: disable user fence interrupt (v2)
amdgpu submits both kernel and user fences, but just need one interrupt,
disable user fence interrupt and don't effect user fence.
v2: fix merge error
Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu.h')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index c33c1af36fa2..37aeed7b454d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h | |||
@@ -317,7 +317,7 @@ struct amdgpu_ring_funcs { | |||
317 | void (*emit_ib)(struct amdgpu_ring *ring, | 317 | void (*emit_ib)(struct amdgpu_ring *ring, |
318 | struct amdgpu_ib *ib); | 318 | struct amdgpu_ib *ib); |
319 | void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, | 319 | void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, |
320 | uint64_t seq, bool write64bit); | 320 | uint64_t seq, unsigned flags); |
321 | bool (*emit_semaphore)(struct amdgpu_ring *ring, | 321 | bool (*emit_semaphore)(struct amdgpu_ring *ring, |
322 | struct amdgpu_semaphore *semaphore, | 322 | struct amdgpu_semaphore *semaphore, |
323 | bool emit_wait); | 323 | bool emit_wait); |
@@ -392,6 +392,9 @@ struct amdgpu_fence_driver { | |||
392 | #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) | 392 | #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) |
393 | #define AMDGPU_FENCE_OWNER_MOVE ((void*)2ul) | 393 | #define AMDGPU_FENCE_OWNER_MOVE ((void*)2ul) |
394 | 394 | ||
395 | #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) | ||
396 | #define AMDGPU_FENCE_FLAG_INT (1 << 1) | ||
397 | |||
395 | struct amdgpu_fence { | 398 | struct amdgpu_fence { |
396 | struct fence base; | 399 | struct fence base; |
397 | 400 | ||
@@ -2142,7 +2145,7 @@ static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) | |||
2142 | #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) | 2145 | #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) |
2143 | #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib)) | 2146 | #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib)) |
2144 | #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) | 2147 | #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) |
2145 | #define amdgpu_ring_emit_fence(r, addr, seq, write64bit) (r)->funcs->emit_fence((r), (addr), (seq), (write64bit)) | 2148 | #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) |
2146 | #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait)) | 2149 | #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait)) |
2147 | #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) | 2150 | #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) |
2148 | #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) | 2151 | #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) |