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authorAndres Rodriguez <andresx7@gmail.com>2017-02-02 00:38:22 -0500
committerAlex Deucher <alexander.deucher@amd.com>2017-05-31 16:48:53 -0400
commit78c16834234ec3e3171d7f80446da574f3e8d39b (patch)
tree41cdea018033c202ef184543fdf4c1556aad802a /drivers/gpu/drm/amd/amdgpu/amdgpu.h
parent42794b27cc628d44db28f62f3333bd12416b597f (diff)
drm/amdgpu: allow split of queues with kfd at queue granularity v4
Previously the queue/pipe split with kfd operated with pipe granularity. This patch allows amdgpu to take ownership of an arbitrary set of queues. It also consolidates the last few magic numbers in the compute initialization process into mec_init. v2: support for gfx9 v3: renamed AMDGPU_MAX_QUEUES to AMDGPU_MAX_COMPUTE_QUEUES v4: fix off-by-one in num_mec checks in *_compute_queue_acquire Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu.h')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 8b269f17506c..4b8710b2f459 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -46,6 +46,8 @@
46#include <drm/drm_gem.h> 46#include <drm/drm_gem.h>
47#include <drm/amdgpu_drm.h> 47#include <drm/amdgpu_drm.h>
48 48
49#include <kgd_kfd_interface.h>
50
49#include "amd_shared.h" 51#include "amd_shared.h"
50#include "amdgpu_mode.h" 52#include "amdgpu_mode.h"
51#include "amdgpu_ih.h" 53#include "amdgpu_ih.h"
@@ -897,6 +899,8 @@ struct amdgpu_rlc {
897 u32 *register_restore; 899 u32 *register_restore;
898}; 900};
899 901
902#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
903
900struct amdgpu_mec { 904struct amdgpu_mec {
901 struct amdgpu_bo *hpd_eop_obj; 905 struct amdgpu_bo *hpd_eop_obj;
902 u64 hpd_eop_gpu_addr; 906 u64 hpd_eop_gpu_addr;
@@ -906,6 +910,9 @@ struct amdgpu_mec {
906 u32 num_pipe_per_mec; 910 u32 num_pipe_per_mec;
907 u32 num_queue_per_pipe; 911 u32 num_queue_per_pipe;
908 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1]; 912 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
913
914 /* These are the resources for which amdgpu takes ownership */
915 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
909}; 916};
910 917
911struct amdgpu_kiq { 918struct amdgpu_kiq {