Merge tag 'drm-next-2018-10-24' of git://anongit.freedesktop.org/drm/drm

Pull drm updates from Dave Airlie:
 "This is going to rebuild more than drm as it adds a new helper to
  list.h for doing bulk updates. Seemed like a reasonable addition to
  me.

  Otherwise the usual merge window stuff lots of i915 and amdgpu, not so
  much nouveau, and piles of everything else.

  Core:
   - Adds a new list.h helper for doing bulk list updates for TTM.
   - Don't leak fb address in smem_start to userspace (comes with EXPORT
     workaround for people using mali out of tree hacks)
   - udmabuf device to turn memfd regions into dma-buf
   - Per-plane blend mode property
   - ref/unref replacements with get/put
   - fbdev conflicting framebuffers code cleaned up
   - host-endian format variants
   - panel orientation quirk for Acer One 10

  bridge:
   - TI SN65DSI86 chip support

  vkms:
   - GEM support.
   - Cursor support

  amdgpu:
   - Merge amdkfd and amdgpu into one module
   - CEC over DP AUX support
   - Picasso APU support + VCN dynamic powergating
   - Raven2 APU support
   - Vega20 enablement + kfd support
   - ACP powergating improvements
   - ABGR/XBGR display support
   - VCN jpeg support
   - xGMI support
   - DC i2c/aux cleanup
   - Ycbcr 4:2:0 support
   - GPUVM improvements
   - Powerplay and powerplay endian fixes
   - Display underflow fixes

  vmwgfx:
   - Move vmwgfx specific TTM code to vmwgfx
   - Split out vmwgfx buffer/resource validation code
   - Atomic operation rework

  bochs:
   - use more helpers
   - format/byteorder improvements

  qxl:
   - use more helpers

  i915:
   - GGTT coherency getparam
   - Turn off resource streamer API
   - More Icelake enablement + DMC firmware
   - Full PPGTT for Ivybridge, Haswell and Valleyview
   - DDB distribution based on resolution
   - Limited range DP display support

  nouveau:
   - CEC over DP AUX support
   - Initial HDMI 2.0 support

  virtio-gpu:
   - vmap support for PRIME objects

  tegra:
   - Initial Tegra194 support
   - DMA/IOMMU integration fixes

  msm:
   - a6xx perf improvements + clock prefix
   - GPU preemption optimisations
   - a6xx devfreq support
   - cursor support

  rockchip:
   - PX30 support
   - rgb output interface support

  mediatek:
   - HDMI output support on mt2701 and mt7623

  rcar-du:
   - Interlaced modes on Gen3
   - LVDS on R8A77980
   - D3 and E3 SoC support

  hisilicon:
   - misc fixes

  mxsfb:
   - runtime pm support

  sun4i:
   - R40 TCON support
   - Allwinner A64 support
   - R40 HDMI support

  omapdrm:
   - Driver rework changing display pipeline ordering to use common code
   - DMM memory barrier and irq fixes
   - Errata workarounds

  exynos:
   - out-bridge support for LVDS bridge driver
   - Samsung 16x16 tiled format support
   - Plane alpha and pixel blend mode support

  tilcdc:
   - suspend/resume update

  mali-dp:
   - misc updates"

* tag 'drm-next-2018-10-24' of git://anongit.freedesktop.org/drm/drm: (1382 commits)
  firmware/dmc/icl: Add missing MODULE_FIRMWARE() for Icelake.
  drm/i915/icl: Fix signal_levels
  drm/i915/icl: Fix DDI/TC port clk_off bits
  drm/i915/icl: create function to identify combophy port
  drm/i915/gen9+: Fix initial readout for Y tiled framebuffers
  drm/i915: Large page offsets for pread/pwrite
  drm/i915/selftests: Disable shrinker across mmap-exhaustion
  drm/i915/dp: Link train Fallback on eDP only if fallback link BW can fit panel's native mode
  drm/i915: Fix intel_dp_mst_best_encoder()
  drm/i915: Skip vcpi allocation for MSTB ports that are gone
  drm/i915: Don't unset intel_connector->mst_port
  drm/i915: Only reset seqno if actually idle
  drm/i915: Use the correct crtc when sanitizing plane mapping
  drm/i915: Restore vblank interrupts earlier
  drm/i915: Check fb stride against plane max stride
  drm/amdgpu/vcn:Fix uninitialized symbol error
  drm: panel-orientation-quirks: Add quirk for Acer One 10 (S1003)
  drm/amd/amdgpu: Fix debugfs error handling
  drm/amdgpu: Update gc_9_0 golden settings.
  drm/amd/powerplay: update PPtable with DC BTC and Tvr SocLimit fields
  ...

1 files changed, 55 insertions, 649 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 447c4c7a36d6..d0102cfc8efb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -28,6 +28,8 @@
 #ifndef __AMDGPU_H__
 #define __AMDGPU_H__
 
+#include "amdgpu_ctx.h"
+
 #include <linux/atomic.h>
 #include <linux/wait.h>
 #include <linux/list.h>
@@ -69,12 +71,32 @@
 #include "amdgpu_vcn.h"
 #include "amdgpu_mn.h"
 #include "amdgpu_gmc.h"
+#include "amdgpu_gfx.h"
+#include "amdgpu_sdma.h"
 #include "amdgpu_dm.h"
 #include "amdgpu_virt.h"
 #include "amdgpu_gart.h"
 #include "amdgpu_debugfs.h"
 #include "amdgpu_job.h"
 #include "amdgpu_bo_list.h"
+#include "amdgpu_gem.h"
+
+#define MAX_GPU_INSTANCE                16
+
+struct amdgpu_gpu_instance
+{
+        struct amdgpu_device            *adev;
+        int                             mgpu_fan_enabled;
+};
+
+struct amdgpu_mgpu_info
+{
+        struct amdgpu_gpu_instance      gpu_ins[MAX_GPU_INSTANCE];
+        struct mutex                    mutex;
+        uint32_t                        num_gpu;
+        uint32_t                        num_dgpu;
+        uint32_t                        num_apu;
+};
 
 /*
  * Modules parameters.
@@ -129,6 +151,7 @@ extern int amdgpu_compute_multipipe;
 extern int amdgpu_gpu_recovery;
 extern int amdgpu_emu_mode;
 extern uint amdgpu_smu_memory_pool_size;
+extern struct amdgpu_mgpu_info mgpu_info;
 
 #ifdef CONFIG_DRM_AMDGPU_SI
 extern int amdgpu_si_support;
@@ -148,9 +171,6 @@ extern int amdgpu_cik_support;
 #define AMDGPUFB_CONN_LIMIT                     4
 #define AMDGPU_BIOS_NUM_SCRATCH                 16
 
-/* max number of IP instances */
-#define AMDGPU_MAX_SDMA_INSTANCES               2
-
 /* hard reset data */
 #define AMDGPU_ASIC_RESET_DATA                  0x39d5e86b
 
@@ -171,13 +191,6 @@ extern int amdgpu_cik_support;
 #define AMDGPU_RESET_VCE                        (1 << 13)
 #define AMDGPU_RESET_VCE1                       (1 << 14)
 
-/* GFX current status */
-#define AMDGPU_GFX_NORMAL_MODE                  0x00000000L
-#define AMDGPU_GFX_SAFE_MODE                    0x00000001L
-#define AMDGPU_GFX_PG_DISABLED_MODE             0x00000002L
-#define AMDGPU_GFX_CG_DISABLED_MODE             0x00000004L
-#define AMDGPU_GFX_LBPW_DISABLED_MODE           0x00000008L
-
 /* max cursor sizes (in pixels) */
 #define CIK_CURSOR_WIDTH 128
 #define CIK_CURSOR_HEIGHT 128
@@ -205,13 +218,6 @@ enum amdgpu_cp_irq {
         AMDGPU_CP_IRQ_LAST
 };
 
-enum amdgpu_sdma_irq {
-        AMDGPU_SDMA_IRQ_TRAP0 = 0,
-        AMDGPU_SDMA_IRQ_TRAP1,
-
-        AMDGPU_SDMA_IRQ_LAST
-};
-
 enum amdgpu_thermal_irq {
         AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
         AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
@@ -224,6 +230,10 @@ enum amdgpu_kiq_irq {
         AMDGPU_CP_KIQ_IRQ_LAST
 };
 
+#define MAX_KIQ_REG_WAIT       5000 /* in usecs, 5ms */
+#define MAX_KIQ_REG_BAILOUT_INTERVAL   5 /* in msecs, 5ms */
+#define MAX_KIQ_REG_TRY 20
+
 int amdgpu_device_ip_set_clockgating_state(void *dev,
                                            enum amd_ip_block_type block_type,
                                            enum amd_clockgating_state state);
@@ -271,70 +281,6 @@ amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
                                const struct amdgpu_ip_block_version *ip_block_version);
 
-/* provided by hw blocks that can move/clear data.  e.g., gfx or sdma */
-struct amdgpu_buffer_funcs {
-        /* maximum bytes in a single operation */
-        uint32_t        copy_max_bytes;
-
-        /* number of dw to reserve per operation */
-        unsigned        copy_num_dw;
-
-        /* used for buffer migration */
-        void (*emit_copy_buffer)(struct amdgpu_ib *ib,
-                                 /* src addr in bytes */
-                                 uint64_t src_offset,
-                                 /* dst addr in bytes */
-                                 uint64_t dst_offset,
-                                 /* number of byte to transfer */
-                                 uint32_t byte_count);
-
-        /* maximum bytes in a single operation */
-        uint32_t        fill_max_bytes;
-
-        /* number of dw to reserve per operation */
-        unsigned        fill_num_dw;
-
-        /* used for buffer clearing */
-        void (*emit_fill_buffer)(struct amdgpu_ib *ib,
-                                 /* value to write to memory */
-                                 uint32_t src_data,
-                                 /* dst addr in bytes */
-                                 uint64_t dst_offset,
-                                 /* number of byte to fill */
-                                 uint32_t byte_count);
-};
-
-/* provided by hw blocks that can write ptes, e.g., sdma */
-struct amdgpu_vm_pte_funcs {
-        /* number of dw to reserve per operation */
-        unsigned        copy_pte_num_dw;
-
-        /* copy pte entries from GART */
-        void (*copy_pte)(struct amdgpu_ib *ib,
-                         uint64_t pe, uint64_t src,
-                         unsigned count);
-
-        /* write pte one entry at a time with addr mapping */
-        void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
-                          uint64_t value, unsigned count,
-                          uint32_t incr);
-        /* for linear pte/pde updates without addr mapping */
-        void (*set_pte_pde)(struct amdgpu_ib *ib,
-                            uint64_t pe,
-                            uint64_t addr, unsigned count,
-                            uint32_t incr, uint64_t flags);
-};
-
-/* provided by the ih block */
-struct amdgpu_ih_funcs {
-        /* ring read/write ptr handling, called from interrupt context */