Merge branch 'queue/irq/gpio' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip into devel

1 files changed, 9 insertions, 10 deletions

diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c
index 86cfe1892cae..7be269402baf 100644
--- a/drivers/gpio/gpio-davinci.c
+++ b/drivers/gpio/gpio-davinci.c
@@ -65,11 +65,11 @@ static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio)
         return ptr;
 }
 
-static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
+static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
 {
         struct davinci_gpio_regs __iomem *g;
 
-        g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
+        g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
 
         return g;
 }
@@ -287,7 +287,7 @@ static int davinci_gpio_probe(struct platform_device *pdev)
 
 static void gpio_irq_disable(struct irq_data *d)
 {
-        struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
+        struct davinci_gpio_regs __iomem *g = irq2regs(d);
         u32 mask = (u32) irq_data_get_irq_handler_data(d);
 
         writel_relaxed(mask, &g->clr_falling);
@@ -296,7 +296,7 @@ static void gpio_irq_disable(struct irq_data *d)
 
 static void gpio_irq_enable(struct irq_data *d)
 {
-        struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
+        struct davinci_gpio_regs __iomem *g = irq2regs(d);
         u32 mask = (u32) irq_data_get_irq_handler_data(d);
         unsigned status = irqd_get_trigger_type(d);
 
@@ -327,8 +327,9 @@ static struct irq_chip gpio_irqchip = {
 };
 
 static void
-gpio_irq_handler(unsigned irq, struct irq_desc *desc)
+gpio_irq_handler(unsigned __irq, struct irq_desc *desc)
 {
+        unsigned int irq = irq_desc_get_irq(desc);
         struct davinci_gpio_regs __iomem *g;
         u32 mask = 0xffff;
         struct davinci_gpio_controller *d;
@@ -396,7 +397,7 @@ static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
         struct davinci_gpio_regs __iomem *g;
         u32 mask;
 
-        d = (struct davinci_gpio_controller *)data->handler_data;
+        d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
         g = (struct davinci_gpio_regs __iomem *)d->regs;
         mask = __gpio_mask(data->irq - d->gpio_irq);
 
@@ -578,15 +579,13 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
                 writel_relaxed(~0, &g->clr_falling);
                 writel_relaxed(~0, &g->clr_rising);
 
-                /* set up all irqs in this bank */
-                irq_set_chained_handler(bank_irq, gpio_irq_handler);
-
                 /*
                  * Each chip handles 32 gpios, and each irq bank consists of 16
                  * gpio irqs. Pass the irq bank's corresponding controller to
                  * the chained irq handler.
                  */
-                irq_set_handler_data(bank_irq, &chips[gpio / 32]);
+                irq_set_chained_handler_and_data(bank_irq, gpio_irq_handler,
+                                                 &chips[gpio / 32]);
 
                 binten |= BIT(bank);
         }