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authorLinus Torvalds <torvalds@linux-foundation.org>2017-11-14 20:23:44 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2017-11-14 20:23:44 -0500
commit6aa2f9441f1ef21f10c41f45e6453b135e9cd736 (patch)
tree334e67c4693eddff47a098b9afad63ca2ccfcd55 /drivers/gpio/gpio-aspeed.c
parente37e0ee0190034a059c9faea8adfb4982fb24ddd (diff)
parent24f0966c3e3f52a96e888504d60810d9df5b2d42 (diff)
Merge tag 'gpio-v4.15-1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull GPIO updates from Linus Walleij: "This is the bulk of GPIO changes for the v4.15 kernel cycle: Core: - Fix the semantics of raw GPIO to actually be raw. No inversion semantics as before, but also no open draining, and allow the raw operations to affect lines used for interrupts as the caller supposedly knows what they are doing if they are getting the big hammer. - Rewrote the __inner_function() notation calls to names that make more sense. I just find this kind of code disturbing. - Drop the .irq_base() field from the gpiochip since now all IRQs are mapped dynamically. This is nice. - Support for .get_multiple() in the core driver API. This allows us to read several GPIO lines with a single register read. This has high value for some usecases: it can be used to create oscilloscopes and signal analyzers and other things that rely on reading several lines at exactly the same instant. Also a generally nice optimization. This uses the new assign_bit() macro from the bitops lib that was ACKed by Andrew Morton and is implemented for two drivers, one of them being the generic MMIO driver so everyone using that will be able to benefit from this. - Do not allow requests of Open Drain and Open Source setting of a GPIO line simultaneously. If the hardware actually supports enabling both at the same time the electrical result would be disastrous. - A new interrupt chip core helper. This will be helpful to deal with "banked" GPIOs, which means GPIO controllers with several logical blocks of GPIO inside them. This is several gpiochips per device in the device model, in contrast to the case when there is a 1-to-1 relationship between a device and a gpiochip. New drivers: - Maxim MAX3191x industrial serializer, a very interesting piece of professional I/O hardware. - Uniphier GPIO driver. This is the GPIO block from the recent Socionext (ex Fujitsu and Panasonic) platform. - Tegra 186 driver. This is based on the new banked GPIO infrastructure. Other improvements: - Some documentation improvements. - Wakeup support for the DesignWare DWAPB GPIO controller. - Reset line support on the DesignWare DWAPB GPIO controller. - Several non-critical bug fixes and improvements for the Broadcom BRCMSTB driver. - Misc non-critical bug fixes like exotic errorpaths, removal of dead code etc. - Explicit comments on fall-through switch() statements" * tag 'gpio-v4.15-1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (65 commits) gpio: tegra186: Remove tegra186_gpio_lock_class gpio: rcar: Add r8a77995 (R-Car D3) support pinctrl: bcm2835: Fix some merge fallout gpio: Fix undefined lock_dep_class gpio: Automatically add lockdep keys gpio: Introduce struct gpio_irq_chip.first gpio: Disambiguate struct gpio_irq_chip.nested gpio: Add Tegra186 support gpio: Export gpiochip_irq_{map,unmap}() gpio: Implement tighter IRQ chip integration gpio: Move lock_key into struct gpio_irq_chip gpio: Move irq_valid_mask into struct gpio_irq_chip gpio: Move irq_nested into struct gpio_irq_chip gpio: Move irq_chained_parent to struct gpio_irq_chip gpio: Move irq_default_type to struct gpio_irq_chip gpio: Move irq_handler to struct gpio_irq_chip gpio: Move irqdomain into struct gpio_irq_chip gpio: Move irqchip into struct gpio_irq_chip gpio: Introduce struct gpio_irq_chip pinctrl: armada-37xx: remove unused variable ...
Diffstat (limited to 'drivers/gpio/gpio-aspeed.c')
-rw-r--r--drivers/gpio/gpio-aspeed.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c
index bfc53995064a..8781817d9003 100644
--- a/drivers/gpio/gpio-aspeed.c
+++ b/drivers/gpio/gpio-aspeed.c
@@ -411,13 +411,16 @@ static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type)
411 switch (type & IRQ_TYPE_SENSE_MASK) { 411 switch (type & IRQ_TYPE_SENSE_MASK) {
412 case IRQ_TYPE_EDGE_BOTH: 412 case IRQ_TYPE_EDGE_BOTH:
413 type2 |= bit; 413 type2 |= bit;
414 /* fall through */
414 case IRQ_TYPE_EDGE_RISING: 415 case IRQ_TYPE_EDGE_RISING:
415 type0 |= bit; 416 type0 |= bit;
417 /* fall through */
416 case IRQ_TYPE_EDGE_FALLING: 418 case IRQ_TYPE_EDGE_FALLING:
417 handler = handle_edge_irq; 419 handler = handle_edge_irq;
418 break; 420 break;
419 case IRQ_TYPE_LEVEL_HIGH: 421 case IRQ_TYPE_LEVEL_HIGH:
420 type0 |= bit; 422 type0 |= bit;
423 /* fall through */
421 case IRQ_TYPE_LEVEL_LOW: 424 case IRQ_TYPE_LEVEL_LOW:
422 type1 |= bit; 425 type1 |= bit;
423 handler = handle_level_irq; 426 handler = handle_level_irq;
@@ -466,7 +469,7 @@ static void aspeed_gpio_irq_handler(struct irq_desc *desc)
466 reg = ioread32(bank_irq_reg(data, bank, GPIO_IRQ_STATUS)); 469 reg = ioread32(bank_irq_reg(data, bank, GPIO_IRQ_STATUS));
467 470
468 for_each_set_bit(p, &reg, 32) { 471 for_each_set_bit(p, &reg, 32) {
469 girq = irq_find_mapping(gc->irqdomain, i * 32 + p); 472 girq = irq_find_mapping(gc->irq.domain, i * 32 + p);
470 generic_handle_irq(girq); 473 generic_handle_irq(girq);
471 } 474 }
472 475
@@ -498,7 +501,7 @@ static void set_irq_valid_mask(struct aspeed_gpio *gpio)
498 if (i >= gpio->config->nr_gpios) 501 if (i >= gpio->config->nr_gpios)
499 break; 502 break;
500 503
501 clear_bit(i, gpio->chip.irq_valid_mask); 504 clear_bit(i, gpio->chip.irq.valid_mask);
502 } 505 }
503 506
504 props++; 507 props++;
@@ -853,7 +856,7 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev)
853 gpio->chip.set_config = aspeed_gpio_set_config; 856 gpio->chip.set_config = aspeed_gpio_set_config;
854 gpio->chip.label = dev_name(&pdev->dev); 857 gpio->chip.label = dev_name(&pdev->dev);
855 gpio->chip.base = -1; 858 gpio->chip.base = -1;
856 gpio->chip.irq_need_valid_mask = true; 859 gpio->chip.irq.need_valid_mask = true;
857 860
858 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); 861 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
859 if (rc < 0) 862 if (rc < 0)