Merge tag 'gpio-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio

Pull GPIO updates from Linus Walleij:
 "This is the bulk of GPIO changes for the v4.12 kernel cycle.

  Core changes:

   - Return NULL from gpiod_get_optional() when GPIOLIB is disabled.
     This was a much discussed change. It affects use cases where people
     write drivers that might or might not be using GPIO resources. I
     have decided that this is the lesser evil right now.

   - Make gpiod_count() behave consistently across different hardware
     descriptions.

   - Fix the syntax around open drain/open source to not infer active
     high/low semantics.

  New drivers:

   - A new single-register fixed-direction framework driver for hardware
     that have lines controlled by a single register that just work in
     one direction (out or in), including IRQ support.

   - Support the Fintek F71889A GPIO SuperIO controller.

   - Support the National NI 169445 MMIO GPIO.

   - Support for the X-Gene derivative of the DWC GPIO controller

   - Support for the Rohm BD9571MWV-M PMIC GPIO controller.

   - Refactor the Gemini GPIO driver to a generic Faraday FTGPIO driver
     and replace both the Gemini and the Moxa ART custom drivers with
     this driver.

  Driver improvements:

   - A whole slew of drivers have their spinlocks chaned to raw
     spinlocks as they provide irqchips, and thus we are progressing on
     realtime compliance.

   - Use devm_irq_alloc_descs() in a slew of drivers, getting managed
     resources.

   - Support for the embedded PWM controller inside the MVEBU driver.

   - Debounce, open source and open drain support for the Aspeed driver.

   - Misc smaller fixes like spelling and syntax and whatnot"

* tag 'gpio-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (77 commits)
  gpio: f7188x: Add a missing break
  gpio: omap: return error if requested debounce time is not possible
  gpio: Add ROHM BD9571MWV-M PMIC GPIO driver
  gpio: gpio-wcove: fix GPIO IRQ status mask
  gpio: DT bindings, move tca9554 from pcf857x to pca953x
  gpio: move tca9554 from pcf857x to pca953x
  gpio: arizona: Correct check whether the pin is an input
  gpio: Add XRA1403 DTS binding documentation
  dt-bindings: add exar to vendor prefixes list
  gpio: gpio-wcove: fix irq pending status bit width
  gpio: dwapb: use dwapb_read instead of readl_relaxed
  gpio: aspeed: Add open-source and open-drain support
  gpio: aspeed: Add debounce support
  gpio: aspeed: dt: Add optional clocks property
  gpio: aspeed: dt: Fix description alignment in bindings document
  gpio: mvebu: Add limited PWM support
  gpio: Use unsigned int for interrupt numbers
  gpio: f7188x: Add F71889A GPIO support.
  gpio: core: Decouple open drain/source flag with active low/high
  gpio: arizona: Correct handling for reading input GPIOs
  ...

1 files changed, 12 insertions, 12 deletions

diff --git a/drivers/gpio/gpio-altera.c b/drivers/gpio/gpio-altera.c
index 3fe6a21e05a5..17485dc20384 100644
--- a/drivers/gpio/gpio-altera.c
+++ b/drivers/gpio/gpio-altera.c
@@ -38,7 +38,7 @@
 */
 struct altera_gpio_chip {
         struct of_mm_gpio_chip mmchip;
-        spinlock_t gpio_lock;
+        raw_spinlock_t gpio_lock;
         int interrupt_trigger;
         int mapped_irq;
 };
@@ -53,12 +53,12 @@ static void altera_gpio_irq_unmask(struct irq_data *d)
         altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
         mm_gc = &altera_gc->mmchip;
 
-        spin_lock_irqsave(&altera_gc->gpio_lock, flags);
+        raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
         intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
         /* Set ALTERA_GPIO_IRQ_MASK bit to unmask */
         intmask |= BIT(irqd_to_hwirq(d));
         writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
-        spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
+        raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
 }
 
 static void altera_gpio_irq_mask(struct irq_data *d)
@@ -71,12 +71,12 @@ static void altera_gpio_irq_mask(struct irq_data *d)
         altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
         mm_gc = &altera_gc->mmchip;
 
-        spin_lock_irqsave(&altera_gc->gpio_lock, flags);
+        raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
         intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
         /* Clear ALTERA_GPIO_IRQ_MASK bit to mask */
         intmask &= ~BIT(irqd_to_hwirq(d));
         writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
-        spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
+        raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
 }
 
 /**
@@ -140,14 +140,14 @@ static void altera_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
         mm_gc = to_of_mm_gpio_chip(gc);
         chip = gpiochip_get_data(gc);
 
-        spin_lock_irqsave(&chip->gpio_lock, flags);
+        raw_spin_lock_irqsave(&chip->gpio_lock, flags);
         data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
         if (value)
                 data_reg |= BIT(offset);
         else
                 data_reg &= ~BIT(offset);
         writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
-        spin_unlock_irqrestore(&chip->gpio_lock, flags);
+        raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
 }
 
 static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
@@ -160,12 +160,12 @@ static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
         mm_gc = to_of_mm_gpio_chip(gc);
         chip = gpiochip_get_data(gc);
 
-        spin_lock_irqsave(&chip->gpio_lock, flags);
+        raw_spin_lock_irqsave(&chip->gpio_lock, flags);
         /* Set pin as input, assumes software controlled IP */
         gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
         gpio_ddr &= ~BIT(offset);
         writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
-        spin_unlock_irqrestore(&chip->gpio_lock, flags);
+        raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
 
         return 0;
 }
@@ -181,7 +181,7 @@ static int altera_gpio_direction_output(struct gpio_chip *gc,
         mm_gc = to_of_mm_gpio_chip(gc);
         chip = gpiochip_get_data(gc);
 
-        spin_lock_irqsave(&chip->gpio_lock, flags);
+        raw_spin_lock_irqsave(&chip->gpio_lock, flags);
         /* Sets the GPIO value */
         data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
         if (value)
@@ -194,7 +194,7 @@ static int altera_gpio_direction_output(struct gpio_chip *gc,
         gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
         gpio_ddr |= BIT(offset);
         writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
-        spin_unlock_irqrestore(&chip->gpio_lock, flags);
+        raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
 
         return 0;
 }
@@ -262,7 +262,7 @@ static int altera_gpio_probe(struct platform_device *pdev)
         if (!altera_gc)
                 return -ENOMEM;
 
-        spin_lock_init(&altera_gc->gpio_lock);
+        raw_spin_lock_init(&altera_gc->gpio_lock);
 
         if (of_property_read_u32(node, "altr,ngpio", &reg))
                 /* By default assume maximum ngpio */